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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id q9-20020a056512210900b005079691360csm2978277lfr.49.2023.10.26.04.06.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Oct 2023 04:06:56 -0700 (PDT) Message-ID: <8dc48acb-46f0-47fa-bf7f-ee2d09eebcb3@linaro.org> Date: Thu, 26 Oct 2023 13:06:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP Content-Language: en-US To: Sibi Sankar , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: agross@kernel.org, conor+dt@kernel.org, quic_tdas@quicinc.com, quic_rjendra@quicinc.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, quic_tsoni@quicinc.com References: <20231025133320.4720-1-quic_sibis@quicinc.com> <20231025133320.4720-3-quic_sibis@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231025133320.4720-3-quic_sibis@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 26 Oct 2023 04:07:06 -0700 (PDT) On 10/25/23 15:33, Sibi Sankar wrote: > From: Rajendra Nayak > > Add support for the global clock controller found on SC8380XP > based devices. > > Co-developed-by: Abel Vesa > Signed-off-by: Abel Vesa > Signed-off-by: Rajendra Nayak > Signed-off-by: Sibi Sankar > --- [...] > +static int gcc_sc8380xp_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + regmap = qcom_cc_map(pdev, &gcc_sc8380xp_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, > + ARRAY_SIZE(gcc_dfs_clocks)); > + if (ret) > + return ret; > + > + /* > + * Keep the critical clock always-On > + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, > + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, > + * gcc_video_xo_clk > + */ > + regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); Please inline the clock names, like so: regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ LGTM otherwise Konrad