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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v18-20020a05683018d200b006b9cc67386fsm18867ote.66.2023.10.26.14.25.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 14:25:48 -0700 (PDT) Received: (nullmailer pid 424302 invoked by uid 1000); Thu, 26 Oct 2023 21:25:46 -0000 Date: Thu, 26 Oct 2023 16:25:46 -0500 From: Rob Herring To: Tao Zhang Cc: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Krzysztof Kozlowski , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Song Chai , linux-arm-msm@vger.kernel.org, andersson@kernel.org Subject: Re: [PATCH v2 1/8] dt-bindings: arm: Add support for CMB element size Message-ID: <20231026212546.GA420866-robh@kernel.org> References: <1698202408-14608-1-git-send-email-quic_taozha@quicinc.com> <1698202408-14608-2-git-send-email-quic_taozha@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1698202408-14608-2-git-send-email-quic_taozha@quicinc.com> X-Spam-Status: No, score=-1.0 required=5.0 tests=MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 26 Oct 2023 14:26:02 -0700 (PDT) On Wed, Oct 25, 2023 at 10:53:21AM +0800, Tao Zhang wrote: > Add property "qcom,cmb-elem-size" to support CMB(Continuous > Multi-Bit) element for TPDM. The associated aggregator will read > this size before it is enabled. CMB element size currently only > supports 32-bit and 64-bit. > > Signed-off-by: Tao Zhang > Signed-off-by: Mao Jinlong > --- > .../bindings/arm/qcom,coresight-tpdm.yaml | 27 ++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index 61ddc3b..f9a2025 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -52,6 +52,14 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint8 > enum: [32, 64] > > + qcom,cmb-element-size: What are the units? Use '-bits' suffix. > + description: > + Specifies the CMB(Continuous Multi-Bit) element size supported by > + the monitor. The associated aggregator will read this size before it > + is enabled. CMB element size currently only supports 32-bit and 64-bit. The enum says 8-bit is supported. > + $ref: /schemas/types.yaml#/definitions/uint8 > + enum: [8, 32, 64] > + > qcom,dsb-msrs-num: > description: > Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) > @@ -110,4 +118,23 @@ examples: > }; > }; > > + tpdm@6c29000 { > + compatible = "qcom,coresight-tpdm", "arm,primecell"; > + reg = <0x06c29000 0x1000>; > + reg-names = "tpdm-base"; > + > + qcom,cmb-element-size = /bits/ 8 <64>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + tpdm_ipcc_out_funnel_center: endpoint { > + remote-endpoint = > + <&funnel_center_in_tpdm_ipcc>; > + }; > + }; > + }; > + }; > ... > -- > 2.7.4 >