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Subject: Re: [PATCH v4 0/4] rockchip: add GATE_LINK
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     conor+dt@kernel.org, heiko@sntech.de, kever.yang@rock-chips.com,
        krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
        robh+dt@kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
        linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
        huangtao@rock-chips.com, andy.yan@rock-chips.com
To:     Sebastian Reichel <sebastian.reichel@collabora.com>,
        zhangqing <zhangqing@rock-chips.com>
Date:   Thu, 26 Oct 2023 14:29:44 -0700
User-Agent: alot/0.10
Precedence: bulk

Quoting zhangqing (2023-10-25 19:25:43)
>=20
> =E5=9C=A8 2023/10/26 5:40, Stephen Boyd =E5=86=99=E9=81=93:
> > Quoting Sebastian Reichel (2023-10-25 12:48:49)
> >> Hello Stephen,
> >>
> >> On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote:
> >>> Quoting Elaine Zhang (2023-10-18 00:01:40)
> >>>> Recent Rockchip SoCs have a new hardware block called Native Interfa=
ce
> >>>> Unit (NIU), which gates clocks to devices behind them. These effecti=
vely
> >>>> need two parent clocks.
> >>>> Use GATE_LINK to handle this.
> >>> Why can't pm clks be used here? The qcom clk driver has been doing th=
at
> >>> for some time now.
> >>>
> >>>   $ git grep pm_clk_add -- drivers/clk/qcom/
> >> Maybe I'm mistaken, but as far as I can tell this is adding the
> >> dependency on controller level and only works because Qualcomm
> >> has multiple separate clock controllers. In the Rockchip design
> >> there is only one platform device.
> >>
> >> Note, that the original downstream code from Rockchip actually used
> >> pm_clk infrastructure by moving these clocks to separate platform
> >> devices. I changed this when upstreaming the code, since that leaks
> >> into DT and from DT point of view there should be only one clock
> >> controller.
> >>
> > Why can't the rockchip driver bind to a single device node and make
> > sub-devices for each clk domain and register clks for those? Maybe it
> > can use the auxiliary driver infrastructure to do that?
>=20
> Option 1:
>=20
> Use the current patch to adapt the GATE_LINK type upstream.
>=20
> The real function of GATE_LINK is implemented=E3=80=82
>=20
> Just to improve and adapt the existing features on upstream.
>=20
>=20
> Option 2:
>=20
> What we use on our internal branches are:

Does this require DT changes? If so, it's a non-starter. Why can't
auxiliary devices be used?