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From:   Linhua Xu <Linhua.xu@unisoc.com>
To:     Linus Walleij <linus.walleij@linaro.org>
CC:     Orson Zhai <orsonzhai@gmail.com>,
        Baolin Wang <baolin.wang@linux.alibaba.com>,
        Chunyan Zhang <zhang.lyra@gmail.com>,
        <linux-kernel@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        lh xu <xulh0829@gmail.com>, Linhua Xu <Linhua.Xu@unisoc.com>,
        Zhirong Qiu <zhirong.qiu@unisoc.com>,
        Xiongpeng Wu <xiongpeng.wu@unisoc.com>
Subject: [PATCH V3 4/6] pinctrl: sprd: Increase the range of register values
Date:   Fri, 27 Oct 2023 15:14:24 +0800
Message-ID: <20231027071426.17724-5-Linhua.xu@unisoc.com>
In-Reply-To: <20231027071426.17724-1-Linhua.xu@unisoc.com>
References: <20231027071426.17724-1-Linhua.xu@unisoc.com>
MIME-Version: 1.0
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From: Linhua Xu <Linhua.Xu@unisoc.com>

As the UNISOC pin controller version iterates, more registers are required
to meet new functional requirements. Thus modify them.

Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
 drivers/pinctrl/sprd/pinctrl-sprd.h | 44 +++++++++++++++++------------
 1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
index 23bced4665f1..a6ba75313da0 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.h
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
@@ -7,30 +7,38 @@
 #ifndef __PINCTRL_SPRD_H__
 #define __PINCTRL_SPRD_H__
 
+#include <linux/bits.h>
+
 struct platform_device;
 
-#define NUM_OFFSET	(20)
-#define TYPE_OFFSET	(16)
-#define BIT_OFFSET	(8)
-#define WIDTH_OFFSET	(4)
+#define NUM_OFFSET	22
+#define TYPE_OFFSET	18
+#define BIT_OFFSET	10
+#define WIDTH_OFFSET	6
+
+#define NUM_MASK	GENMASK(10, 0)
+#define TYPE_MASK	GENMASK(3, 0)
+#define BIT_MASK	GENMASK(7, 0)
+#define WIDTH_MASK	GENMASK(3, 0)
+#define REG_MASK	GENMASK(5, 0)
 
-#define SPRD_PIN_INFO(num, type, offset, width, reg)	\
-		(((num) & 0xFFF) << NUM_OFFSET |	\
-		 ((type) & 0xF) << TYPE_OFFSET |	\
-		 ((offset) & 0xFF) << BIT_OFFSET |	\
-		 ((width) & 0xF) << WIDTH_OFFSET |	\
-		 ((reg) & 0xF))
+#define SPRD_PIN_INFO(num, type, offset, width, reg)		\
+		(((num) & NUM_MASK) << NUM_OFFSET |		\
+		 ((type) & TYPE_MASK) << TYPE_OFFSET |		\
+		 ((offset) & BIT_MASK) << BIT_OFFSET |		\
+		 ((width) & WIDTH_MASK) << WIDTH_OFFSET |	\
+		 ((reg) & REG_MASK))
 
 #define SPRD_PINCTRL_PIN(pin)	SPRD_PINCTRL_PIN_DATA(pin, #pin)
 
-#define SPRD_PINCTRL_PIN_DATA(a, b)				\
-	{							\
-		.name = b,					\
-		.num = (((a) >> NUM_OFFSET) & 0xfff),		\
-		.type = (((a) >> TYPE_OFFSET) & 0xf),		\
-		.bit_offset = (((a) >> BIT_OFFSET) & 0xff),	\
-		.bit_width = ((a) >> WIDTH_OFFSET & 0xf),	\
-		.reg = ((a) & 0xf)				\
+#define SPRD_PINCTRL_PIN_DATA(a, b)					\
+	{								\
+		.name = b,						\
+		.num = (((a) >> NUM_OFFSET) & NUM_MASK),		\
+		.type = (((a) >> TYPE_OFFSET) & TYPE_MASK),		\
+		.bit_offset = (((a) & BIT_OFFSET) & BIT_MASK),		\
+		.bit_width = (((a) & WIDTH_OFFSET) & WIDTH_MASK),	\
+		.reg = ((a) & REG_MASK)					\
 	}
 
 enum pin_type {
-- 
2.17.1