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Fri, 27 Oct 2023 09:03:42 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39R93flv028162 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Oct 2023 09:03:41 GMT Received: from [10.214.66.81] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 27 Oct 2023 02:03:38 -0700 Message-ID: Date: Fri, 27 Oct 2023 14:33:32 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v8 2/3] firmware: scm: Modify only the download bits in TCSR register Content-Language: en-US To: Elliot Berman , , , , CC: , , , Poovendhan Selvaraj References: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> <1698235506-16993-3-git-send-email-quic_mojha@quicinc.com> <8b0d1ab1-e4e6-4152-bcb6-c83909060652@quicinc.com> From: Mukesh Ojha In-Reply-To: <8b0d1ab1-e4e6-4152-bcb6-c83909060652@quicinc.com> Content-Type: text/plain; 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Fri, 27 Oct 2023 02:04:04 -0700 (PDT) On 10/26/2023 5:23 AM, Elliot Berman wrote: > > > On 10/25/2023 5:05 AM, Mukesh Ojha wrote: >> Crashdump collection is done based on DLOAD bits of TCSR register. >> To retain other bits, scm driver need to read the register and >> modify only the DLOAD bits, as other bits in TCSR may have their >> own significance. >> >> Co-developed-by: Poovendhan Selvaraj >> Signed-off-by: Poovendhan Selvaraj >> Signed-off-by: Mukesh Ojha >> Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 >> Reviewed-by: Dmitry Baryshkov >> --- >> drivers/firmware/qcom/qcom_scm.c | 12 ++++++++++-- >> 1 file changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c >> index 25549178a30f..f1c4a9f9a53f 100644 >> --- a/drivers/firmware/qcom/qcom_scm.c >> +++ b/drivers/firmware/qcom/qcom_scm.c >> @@ -4,6 +4,8 @@ >> */ >> >> #include >> +#include >> +#include >> #include >> #include >> #include >> @@ -117,6 +119,10 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { >> #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0) >> #define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1) >> >> +#define QCOM_DLOAD_MASK GENMASK(5, 4) >> +#define QCOM_DLOAD_FULLDUMP 0x1 >> +#define QCOM_DLOAD_NODUMP 0x0 >> + > > > Enum would be better here for related constants. > > diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c > index f1c4a9f9a53f..95f73a8c51d7 100644 > --- a/drivers/firmware/qcom/qcom_scm.c > +++ b/drivers/firmware/qcom/qcom_scm.c > @@ -122,4 +122,6 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { > #define QCOM_DLOAD_MASK GENMASK(5, 4) > -#define QCOM_DLOAD_FULLDUMP 0x1 > -#define QCOM_DLOAD_NODUMP 0x0 > +enum qcom_dload_mode { > + QCOM_DLOAD_NODUMP = 0, > + QCOM_DLOAD_FULLDUMP = 1, > +}; Would it be fine, if i do it during when i add some more modes with minidump ? Please ack, otherwise, will send another version. -Mukesh > > > >> static const char * const qcom_scm_convention_names[] = { >> [SMC_CONVENTION_UNKNOWN] = "unknown", >> [SMC_CONVENTION_ARM_32] = "smc arm 32", >> @@ -523,6 +529,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) >> >> static void qcom_scm_set_download_mode(bool enable) >> { >> + u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP; >> bool avail; >> int ret = 0; >> >> @@ -532,8 +539,9 @@ static void qcom_scm_set_download_mode(bool enable) >> if (avail) { >> ret = __qcom_scm_set_dload_mode(__scm->dev, enable); >> } else if (__scm->dload_mode_addr) { >> - ret = qcom_scm_io_writel(__scm->dload_mode_addr, >> - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); >> + ret = qcom_scm_io_rmw(__scm->dload_mode_addr, >> + QCOM_DLOAD_MASK, >> + FIELD_PREP(QCOM_DLOAD_MASK, val)); >> } else { >> dev_err(__scm->dev, >> "No available mechanism for setting download mode\n"); > > - Elliot