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Sender: Guenter Roeck <groeck7@gmail.com>
Date:   Fri, 27 Oct 2023 08:05:09 -0700
From:   Guenter Roeck <linux@roeck-us.net>
To:     Lakshmi Yadlapati <lakshmiy@us.ibm.com>
Cc:     joel@jms.id.au, andrew@aj.id.au, eajames@linux.ibm.com,
        ninad@linux.ibm.com, jdelvare@suse.com,
        linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5] hwmon: (pmbus/max31785) Add delay between bus accesses
Message-ID: <629a994a-6047-4989-8b22-c36fa7167d10@roeck-us.net>
References: <20231027044346.2167548-1-lakshmiy@us.ibm.com>
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On Thu, Oct 26, 2023 at 11:43:46PM -0500, Lakshmi Yadlapati wrote:
> The MAX31785 has shown erratic behaviour across multiple system
> designs, unexpectedly clock stretching and NAKing transactions.
> 
> Experimentation shows that this seems to be triggered by a register access
> directly back to back with a previous register write. Experimentation also
> shows that inserting a small delay after register writes makes the issue go
> away.
> 
> Use a similar solution to what the max15301 driver does to solve the same
> problem. Create a custom set of bus read and write functions that make sure
> that the delay is added.
> 
> Signed-off-by: Lakshmi Yadlapati <lakshmiy@us.ibm.com>
[ ... ]
> +	if (delta < MAX31785_WAIT_DELAY_US)
> +		usleep_range(MAX31785_WAIT_DELAY_US - delta,
> +			     MAX31785_WAIT_DELAY_US);

This means the driver will now wait up to 250 uS even if it only
has to wait for 1 uS. But I really don't want to wait or argue further,
so I just applied the patch as-is.

Guenter