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Date:   Fri, 27 Oct 2023 16:18:51 +0100
Message-ID: <864jic3xgk.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Thomas Gleixner <tglx@linutronix.de>,
        Fang Xiang <fangxiang3@xiaomi.com>
Cc:     linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.
In-Reply-To: <87v8as32fa.ffs@tglx>
References: <20231027031007.2088-1-fangxiang3@xiaomi.com>
        <87v8as32fa.ffs@tglx>
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On Fri, 27 Oct 2023 09:16:57 +0100,
Thomas Gleixner <tglx@linutronix.de> wrote:
> 
> On Fri, Oct 27 2023 at 11:10, Fang Xiang wrote:
> > In non-coherent GIC design, ITS tables should be clean and flushed
> > to the PoV of the ITS before writing GITS_BASER<n> registers. And
> > hoist the quirked non-shareable attributes earlier to save effort
> > in tables setup.
> >
> > Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
> 
> Seriously? You claim authorship for a patch which was written by Marc:
> 
>    https://lore.kernel.org/all/87sf5x6cdu.wl-maz@kernel.org
> 
> without even the courtesy of giving him credit via 'Originally-by' ?
> 
> That's not how it works.

Even better, some testing results on this patch, as it is what was
promised. Meh...

	M.

-- 
Without deviation from the norm, progress is not possible.