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Date:   Fri, 27 Oct 2023 20:56:41 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     Borislav Petkov <bp@alien8.de>
Cc:     X86 ML <x86@kernel.org>,
        Kishon VijayAbraham <Kishon.VijayAbraham@amd.com>,
        LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] x86/barrier: Do not serialize MSR accesses on AMD
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On Fri, Oct 27, 2023 at 05:34:58PM +0200, Borislav Petkov wrote:

> +static inline void weak_wrmsr_fence(void)
> +{
> +	alternative("mfence; lfence", "", ALT_VENDOR(X86_VENDOR_AMD));
> +}

Well, you see, AFAICT the non-serializing MSRs thing is an Intel thing,
so everything !Intel wants this gone, no?

Definitely the Hygon thing wants this right along with AMD, because
that's basically AMD, no?