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Date:   Fri, 27 Oct 2023 21:16:33 +0200
From:   Borislav Petkov <bp@alien8.de>
To:     Peter Zijlstra <peterz@infradead.org>
Cc:     X86 ML <x86@kernel.org>,
        Kishon VijayAbraham <Kishon.VijayAbraham@amd.com>,
        LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] x86/barrier: Do not serialize MSR accesses on AMD
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On Fri, Oct 27, 2023 at 08:56:41PM +0200, Peter Zijlstra wrote:
> Well, you see, AFAICT the non-serializing MSRs thing is an Intel thing,
> so everything !Intel wants this gone, no?
> 
> Definitely the Hygon thing wants this right along with AMD, because
> that's basically AMD, no?

Because of

ce4e240c279a ("x86: add x2apic_wrmsr_fence() to x2apic flush tlb paths")

and it being there since 2009 and getting called unconditionally.

Hygon sure, but the other vendors? I can't even test on some.

Thus the more conservative approach here.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette