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Date:   Fri, 27 Oct 2023 13:55:20 -0700
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Subject: Re: [PATCH v1 1/1] ufs: core: Add host quirk
 QUIRK_MCQ_EXPAND_QUEUE_SLOT
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 <53d7d12bc12237e5f86522faf09876ab08ef7592.camel@mediatek.com>
From:   Bart Van Assche <bvanassche@acm.org>
In-Reply-To: <53d7d12bc12237e5f86522faf09876ab08ef7592.camel@mediatek.com>
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On 10/26/23 20:27, Chun-Hung Wu (巫駿宏) wrote:
> From UFSHCI 4.0 spec "When the head and tail doorbells are equal, the
> queue is empty. *Nothe that this definition means there will always be
> one empty queue entry"
> One of our platform does not keep one empty queue
> entry for CQ full
> case, that's  why we need this patch to fix this corner case.

The UFSHCI driver should make sure that there is always one empty queue
entry. Does "platform" in the above text refer to the SoC that includes
the UFSHCI controller?

What is totally unclear to me is why the following code depends on the
UFSHCI controller type:

+		if (ufshcd_is_mcq_expand_queue_slot(hba))
+			hwq->max_entries = hba->nutrs + 1;
+		else
+			hwq->max_entries = hba->nutrs;

Shouldn't hwq->max_entries = hba->nutrs + 1 be used for all UFSHCI 4.0
controllers?

Thanks,

Bart.