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[23.128.96.36]) by mx.google.com with ESMTPS id d6-20020a17090a8d8600b0027e022bd420si4507702pjo.77.2023.10.28.11.34.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 11:34:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=NeHTGIxh; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 0784780C4284; Sat, 28 Oct 2023 11:34:46 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229450AbjJ1Sei (ORCPT + 99 others); Sat, 28 Oct 2023 14:34:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229446AbjJ1Seh (ORCPT ); Sat, 28 Oct 2023 14:34:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B22BED; Sat, 28 Oct 2023 11:34:35 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1698518073; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=L9szwvGpZuywL6dp6erj+VxB4LJczIuYNLzmOgYi7ek=; b=NeHTGIxh0eQnS0Cd32fVx2YA/vomR+9OypHHPX0kzSm75ZcgiHjdT5M6xPvB/yfVxhmvyi 1sM5E2+wFxlruQYWALPsgD5eb/JjaspdrBL2wRezSKna9SGWO9MOBb4Igi4dWuiSdL7J8W KBK1peI9NTizGLIMF5CiThWAkBB8gcbjwYrcIVHmjs85prEEHC63m34Xome6BvD29jUayP jUxqBLsNBYhe7Ty81wFnmQRAuyXYYK3amh13W8CJo/MoFyPj6O1R4hgm6oLFo7gtTUpJDl w52kC90+HjKSJ6aGvYaMkznAsGmn5sVMF5JWP4E66uS7ulNRlytptMRFUqWX+w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1698518073; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=L9szwvGpZuywL6dp6erj+VxB4LJczIuYNLzmOgYi7ek=; b=ts0KS2ygqcHxtCjXf8TRE5hulx94A+1MZ6UoC0wgNmiBI2U98b5YU4CJ9uHVW40d0kBHVr H19FWn/6gWPjwADA== To: Anup Patel , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: Re: [PATCH v11 07/14] irqchip: Add RISC-V incoming MSI controller early driver In-Reply-To: <20231023172800.315343-8-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> <20231023172800.315343-8-apatel@ventanamicro.com> Date: Sat, 28 Oct 2023 20:34:33 +0200 Message-ID: <871qde1tqe.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Sat, 28 Oct 2023 11:34:46 -0700 (PDT) On Mon, Oct 23 2023 at 22:57, Anup Patel wrote: > +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS > +void imsic_vector_debug_show(struct seq_file *m, > + struct imsic_vector *vec, int ind) > +{ > + unsigned int mcpu = 0, mlocal_id = 0; > + struct imsic_local_priv *lpriv; > + bool move_in_progress = false; > + struct imsic_vector *mvec; > + bool is_enabled = false; > + unsigned long flags; > + > + lpriv = per_cpu_ptr(imsic->lpriv, vec->cpu); > + if (WARN_ON(&lpriv->vectors[vec->local_id] != vec)) > + return; > + > + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); > + if (test_bit(vec->local_id, lpriv->ids_enabled_bitmap)) > + is_enabled = true; > + mvec = lpriv->ids_move[vec->local_id]; > + if (mvec) { > + move_in_progress = true; > + mcpu = mvec->cpu; > + mlocal_id = mvec->local_id; > + } > + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); > + > + seq_printf(m, "%*starget_cpu : %5u\n", ind, "", vec->cpu); > + seq_printf(m, "%*starget_local_id : %5u\n", ind, "", vec->local_id); > + seq_printf(m, "%*sis_reserved : %5u\n", ind, "", > + (vec->local_id <= IMSIC_IPI_ID) ? 1 : 0); > + seq_printf(m, "%*sis_enabled : %5u\n", ind, "", > + (move_in_progress) ? 1 : 0); > + seq_printf(m, "%*sis_move_pending : %5u\n", ind, "", > + (move_in_progress) ? 1 : 0); > + if (move_in_progress) { > + seq_printf(m, "%*smove_cpu : %5u\n", ind, "", mcpu); > + seq_printf(m, "%*smove_local_id : %5u\n", ind, "", mlocal_id); > + } > +} > + > +void imsic_vector_debug_show_summary(struct seq_file *m, int ind) > +{ > + unsigned int cpu, total_avail = 0, total_used = 0; > + struct imsic_global_config *global = &imsic->global; > + struct imsic_local_priv *lpriv; > + unsigned long flags; > + > + for_each_possible_cpu(cpu) { > + lpriv = per_cpu_ptr(imsic->lpriv, cpu); > + > + total_avail += global->nr_ids; > + > + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); > + total_used += bitmap_weight(lpriv->ids_used_bitmap, > + global->nr_ids + 1) - 1; > + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); > + } > + > + seq_printf(m, "%*stotal : %5u\n", ind, "", total_avail); > + seq_printf(m, "%*sused : %5u\n", ind, "", total_used); > + seq_printf(m, "%*s| CPU | tot | usd | vectors\n", ind, " "); > + > + cpus_read_lock(); > + for_each_online_cpu(cpu) { > + lpriv = per_cpu_ptr(imsic->lpriv, cpu); > + > + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); > + total_used = bitmap_weight(lpriv->ids_used_bitmap, > + global->nr_ids + 1) - 1; > + seq_printf(m, "%*s %4d %4u %4u %*pbl\n", ind, " ", > + cpu, global->nr_ids, total_used, > + global->nr_ids + 1, lpriv->ids_used_bitmap); > + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); > + } > + cpus_read_unlock(); This looks very close to the matrix alocator information, just done differently. > +static unsigned int imsic_vector_best_cpu(const struct cpumask *mask, > + unsigned int order) > +{ > + struct imsic_global_config *global = &imsic->global; > + unsigned int cpu, best_cpu, free, maxfree = 0; > + struct imsic_local_priv *lpriv; > + unsigned long flags; > + > + best_cpu = UINT_MAX; > + for_each_cpu(cpu, mask) { > + if (!cpu_online(cpu)) > + continue; > + > + lpriv = per_cpu_ptr(imsic->lpriv, cpu); > + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); > + free = bitmap_weight(lpriv->ids_used_bitmap, > + global->nr_ids + 1); > + free = (global->nr_ids + 1) - free; > + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); > + if (free < BIT(order) || free <= maxfree) > + continue; > + > + best_cpu = cpu; > + maxfree = free; > + } > + > + return best_cpu; Looks very much like what the matrix allocator provides, right? What's the actual reason that you can't use it? Thanks, tglx