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([2600:1700:2000:b002:c988:e7b9:36ab:57c6]) by smtp.gmail.com with ESMTPSA id bl9-20020a05620a1a8900b0076cc4610d0asm1866833qkb.85.2023.10.28.14.27.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 28 Oct 2023 14:27:14 -0700 (PDT) Message-ID: <133b60f7-a71c-4fa2-ae19-4cad05596a23@sifive.com> Date: Sat, 28 Oct 2023 16:27:12 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC Content-Language: en-US To: Palmer Dabbelt , geert@linux-m68k.org Cc: prabhakar.csengg@gmail.com, magnus.damm@gmail.com, conor+dt@kernel.org, Paul Walmsley , aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com References: From: Samuel Holland In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Sat, 28 Oct 2023 14:27:35 -0700 (PDT) Hi Palmer, On 2023-10-27 5:11 PM, Palmer Dabbelt wrote: > On Tue, 03 Oct 2023 05:34:13 PDT (-0700), geert@linux-m68k.org wrote: >> Hi Prabhakar, >> >> On Fri, Sep 29, 2023 at 2:07 AM Prabhakar wrote: >>> From: Lad Prabhakar >>> >>> Enable the configs required by the below IP blocks which are >>> present on RZ/Five SoC: >>> * ADC >>> * CANFD >>> * DMAC >>> * eMMC/SDHI >>> * OSTM >>> * RAVB (+ Micrel PHY) >>> * RIIC >>> * RSPI >>> * SSI (Sound+WM8978 codec) >>> * Thermal >>> * USB (PHY/RESET/OTG) >>> >>> Along with the above some core configs are enabled too, >>> -> CPU frequency scaling as RZ/Five does support this. >>> -> MTD is enabled as RSPI can be connected to flash chips >>> -> Enabled I2C chardev so that it enables userspace to read/write >>>    i2c devices (similar to arm64) >>> -> Thermal configs as RZ/Five SoC does have thermal unit >>> -> GPIO regulator as we might have IP blocks for which voltage >>>    levels are controlled by GPIOs >>> -> OTG configs as RZ/Five USB can support host/function >>> -> Gadget configs so that we can test USB function (as done in arm64 >>>    all the gadget configs are enabled) >>> >>> Signed-off-by: Lad Prabhakar >> >> Reviewed-by: Geert Uytterhoeven >> >> As I expect this to go in through the RISC-V tree, I will let the >> RISC-V people handle any discussion about more options that should be >> made modular instead of builtin. > > I'm pretty much agnostic on that front, so I'm cool just picking up this.  I've > got just patch 5 in my queue for testing, there's a few other things in front of > it but it should show up on for-next soon. Does it make sense to merge this, considering RZ/Five support depends on NONPORTABLE, and therefore cannot be enabled in defconfig anyway? Regards, Samuel