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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Sun, 29 Oct 2023 20:17:25 +0000
Message-ID: <CA+V-a8sjeT3_BR2waskiZ1zCXFi+R2z67R7SznyjV_2+vGzU8A@mail.gmail.com>
Subject: Re: [PATCH v5 2/4] riscv: Improve flush_tlb_range() for hugetlb pages
To:     Alexandre Ghiti <alexghiti@rivosinc.com>
Cc:     Will Deacon <will@kernel.org>,
        "Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com>,
        Andrew Morton <akpm@linux-foundation.org>,
        Nick Piggin <npiggin@gmail.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Mayuresh Chitale <mchitale@ventanamicro.com>,
        Vincent Chen <vincent.chen@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>, linux-arch@vger.kernel.org,
        linux-mm@kvack.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, Samuel Holland <samuel@sholland.org>
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On Thu, Oct 19, 2023 at 3:04=E2=80=AFPM Alexandre Ghiti <alexghiti@rivosinc=
.com> wrote:
>
> flush_tlb_range() uses a fixed stride of PAGE_SIZE and in its current for=
m,
> when a hugetlb mapping needs to be flushed, flush_tlb_range() flushes the
> whole tlb: so set a stride of the size of the hugetlb mapping in order to
> only flush the hugetlb mapping. However, if the hugepage is a NAPOT regio=
n,
> all PTEs that constitute this mapping must be invalidated, so the stride
> size must actually be the size of the PTE.
>
> Note that THPs are directly handled by flush_pmd_tlb_range().
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
>  arch/riscv/mm/tlbflush.c | 31 ++++++++++++++++++++++++++++++-
>  1 file changed, 30 insertions(+), 1 deletion(-)
>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> #
On RZ/Five SMARC

Cheers,
Prabhakar

> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index fa03289853d8..5933744df91a 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -3,6 +3,7 @@
>  #include <linux/mm.h>
>  #include <linux/smp.h>
>  #include <linux/sched.h>
> +#include <linux/hugetlb.h>
>  #include <asm/sbi.h>
>  #include <asm/mmu_context.h>
>
> @@ -147,7 +148,35 @@ void flush_tlb_page(struct vm_area_struct *vma, unsi=
gned long addr)
>  void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
>                      unsigned long end)
>  {
> -       __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE);
> +       unsigned long stride_size;
> +
> +       if (!is_vm_hugetlb_page(vma)) {
> +               stride_size =3D PAGE_SIZE;
> +       } else {
> +               stride_size =3D huge_page_size(hstate_vma(vma));
> +
> +#ifdef CONFIG_RISCV_ISA_SVNAPOT
> +               /*
> +                * As stated in the privileged specification, every PTE i=
n a
> +                * NAPOT region must be invalidated, so reset the stride =
in that
> +                * case.
> +                */
> +               if (has_svnapot()) {
> +                       if (stride_size >=3D PGDIR_SIZE)
> +                               stride_size =3D PGDIR_SIZE;
> +                       else if (stride_size >=3D P4D_SIZE)
> +                               stride_size =3D P4D_SIZE;
> +                       else if (stride_size >=3D PUD_SIZE)
> +                               stride_size =3D PUD_SIZE;
> +                       else if (stride_size >=3D PMD_SIZE)
> +                               stride_size =3D PMD_SIZE;
> +                       else
> +                               stride_size =3D PAGE_SIZE;
> +               }
> +#endif
> +       }
> +
> +       __flush_tlb_range(vma->vm_mm, start, end - start, stride_size);
>  }
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start=
,
> --
> 2.39.2
>