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Date:   Mon, 30 Oct 2023 10:05:08 +0800
From:   Fang Xiang <fangxiang3@xiaomi.com>
To:     Thomas Gleixner <tglx@linutronix.de>
CC:     <maz@kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2] irqchip/gic-v3-its: Flush ITS tables before writing
 GITS_BASER<n> registers in non-coherent GIC designs.
Message-ID: <ZT8PVJ+TQmqEe8fE@oa-fangxiang3.localdomain>
References: <20231027031007.2088-1-fangxiang3@xiaomi.com>
 <87v8as32fa.ffs@tglx>
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On Fri, Oct 27, 2023 at 10:16:57AM +0200, Thomas Gleixner wrote:
> On Fri, Oct 27 2023 at 11:10, Fang Xiang wrote:
> > In non-coherent GIC design, ITS tables should be clean and flushed
> > to the PoV of the ITS before writing GITS_BASER<n> registers. And
> > hoist the quirked non-shareable attributes earlier to save effort
> > in tables setup.
> >
> > Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
> 
> Seriously? You claim authorship for a patch which was written by Marc:
> 
>    https://lore.kernel.org/all/87sf5x6cdu.wl-maz@kernel.org
> 
> without even the courtesy of giving him credit via 'Originally-by' ?
> 
> That's not how it works.
> 
> Thanks,
> 
>         tglx

I am sorry. That's a terrible mistake. Just want to fix this issue as
soon as possible and I am learning how to contribute to the community 
in a right way.