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Mon, 30 Oct 2023 02:49:36 -0700 (PDT) Describe the NSS clock controller node and it's relevant external clocks. Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 42e2e48b2bc3..291f14a3f10a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -15,6 +15,18 @@ / { #size-cells = <2>; clocks { + cmn_pll_nss_clk_200m: cmn-pll-nss-clk-200m { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; + + cmn_pll_nss_clk_300m: cmn-pll-nss-clk-300m { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -473,6 +485,22 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000{ + compatible = "qcom,ipq5332-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&cmn_pll_nss_clk_200m>, + <&cmn_pll_nss_clk_300m>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <&xo_board>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + #power-domain-cells = <1>; + }; }; timer { -- 2.34.1