Received: by 2002:a05:7412:a9a2:b0:e2:908c:2ebd with SMTP id o34csp2627650rdh; Mon, 30 Oct 2023 03:03:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEmUdChNSgbzztVaOzx+AAmVVm5eUxk7W70ftTT0Bnf6MqOSosZ5BaxLunEmop5Ro5uq5wg X-Received: by 2002:a17:90a:3484:b0:27d:310a:b20e with SMTP id p4-20020a17090a348400b0027d310ab20emr6177741pjb.0.1698660199556; Mon, 30 Oct 2023 03:03:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660199; cv=none; d=google.com; s=arc-20160816; b=TkQ+hKicZb2nQ1chiu4yzfqXDDgOxcqmbS0lnPAxkO0I54+i2C3iyjcu7LhAeKDQob yzq2qw97DFt7tgXTKkkCRCdGplYvCZIpCpUUMf6+hgr1KJ4UMyiYxC08rehqo/HDIVoM I4f5vl7hIfKbTFonq1ZX+aR3STVspD3UWf3cThoY5Dl5wSGm8zUlVkCrbBkeEIeaK7yq mWU7iienST3raDGaZM+GIggIpMaiVb5+Fl+10G2ggisioC7XQ3kGGmbey6oZdSzOMWCz 6lf8dW+8OU/pqCcAGYXCHc1zaPfYAMhVBTtMIcqRKcpdksqeRUw/AXxf1ZF6qXuGzVZI FYgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5QjcwvzrebWfLqJww9KhwNbe3Z1/pLAvIef2nvvVTbQ=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=kO/onSjF9tMts+IAG5bKLcPCV9dBPPOQWBdQMrR66bucDun2COFUmEQtYTbNm7+xMA t4k6E1oXq0yk1q+89N8WvmNaxI4mo/+/O64O5rjGTSRzPxW2CmW1D8PfJ3LSdn4TYnyK 9KiNI1wrsdXsdUpqEl2RXzITXo7g8PUc8x9oED/vQQ4ady8kl6GoK49bhkYIjn27LDHA 6hVMcI7Ui9+OWln7S0mAvz9+QAx10yI9IpPyac5Mc4Rp/5ZHwti+O8cjH/UXDElGZV3M Y32751jNTvYZiV5xUS3biIW/XuHqEMJw22A7mFlTZN0cbOob1OlakenoporbzktGF6aj Jb6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=PebvUAjV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Return-Path: Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id s10-20020a17090aad8a00b0027d3ed58c04si4664721pjq.173.2023.10.30.03.03.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:03:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=PebvUAjV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 1950F803200F; Mon, 30 Oct 2023 03:02:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233265AbjJ3KCu (ORCPT + 99 others); Mon, 30 Oct 2023 06:02:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232837AbjJ3KBD (ORCPT ); Mon, 30 Oct 2023 06:01:03 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 794E510D8; Mon, 30 Oct 2023 03:00:34 -0700 (PDT) X-UUID: 25d70d9c770b11ee8051498923ad61e6-20231030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5QjcwvzrebWfLqJww9KhwNbe3Z1/pLAvIef2nvvVTbQ=; b=PebvUAjVmVNoyCfs4qnWA3g0IlZxMn1uxvalhXQ25OYbHFKCsfsOsPmxmQPhhJ0ARHOJzr9WTc3V81R95ptrpUyEVZekHoir9Fr56KvtW4R7H7nX6pqqFt6+0ZEAJGooFzmsg5htN6zxV4dGtYwDbdZV3AWMtTwMSsFgVPgsqZc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:cd16e8ed-fad8-42ad-9aa4-2b2893b629b4,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5f78ec9,CLOUDID:a1c3cb94-10ce-4e4b-85c2-c9b5229ff92b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 25d70d9c770b11ee8051498923ad61e6-20231030 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 435876430; Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:24 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v8 09/16] dt-bindings: media: mediatek: mdp3: add component TCC for MT8195 Date: Mon, 30 Oct 2023 18:00:15 +0800 Message-ID: <20231030100022.9262-10-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:02:58 -0700 (PDT) Add the fundamental hardware configuration of component TCC, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml new file mode 100644 index 000000000000..14ea556d4f82 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Tone Curve Conversion + +maintainers: + - Matthias Brugger + +description: + Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components. + It is used to handle the tone mapping of various gamma curves in order to + achieve HDR10 effects. This helps adapt the content to the color and + brightness range that standard display devices typically support. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tcc + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0x1400b000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + }; -- 2.18.0