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X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="391983159" X-IronPort-AV: E=Sophos;i="6.03,263,1694761200"; d="scan'208";a="391983159" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2023 10:18:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="830743997" X-IronPort-AV: E=Sophos;i="6.03,263,1694761200"; d="scan'208";a="830743997" Received: from rgibson-mobl.amr.corp.intel.com (HELO [10.251.7.5]) ([10.251.7.5]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2023 10:18:22 -0700 Message-ID: <57d63309-51cd-4138-889d-43fbdf5ec790@intel.com> Date: Mon, 30 Oct 2023 10:18:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 13/14] x86/tsc: Mark Secure TSC as reliable clocksource Content-Language: en-US To: Nikunj A Dadhania , linux-kernel@vger.kernel.org, thomas.lendacky@amd.com, x86@kernel.org, kvm@vger.kernel.org Cc: bp@alien8.de, mingo@redhat.com, tglx@linutronix.de, dave.hansen@linux.intel.com, dionnaglaze@google.com, pgonda@google.com, seanjc@google.com, pbonzini@redhat.com References: <20231030063652.68675-1-nikunj@amd.com> <20231030063652.68675-14-nikunj@amd.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 30 Oct 2023 10:18:39 -0700 (PDT) On 10/29/23 23:36, Nikunj A Dadhania wrote: ... > diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c > index 15f97c0abc9d..b0a8546d3703 100644 > --- a/arch/x86/kernel/tsc.c > +++ b/arch/x86/kernel/tsc.c > @@ -1241,7 +1241,7 @@ static void __init check_system_tsc_reliable(void) > tsc_clocksource_reliable = 1; > } > #endif > - if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) > + if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE) || cc_platform_has(CC_ATTR_GUEST_SECURE_TSC)) > tsc_clocksource_reliable = 1; Why can't you just set X86_FEATURE_TSC_RELIABLE?