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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id x10-20020a17090300ca00b001cc0e39373bsi456004plc.32.2023.10.30.12.29.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 12:29:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=OvyHHOlB; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id F39AF80A1A09; Mon, 30 Oct 2023 12:29:34 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231222AbjJ3T3U (ORCPT + 99 others); Mon, 30 Oct 2023 15:29:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229626AbjJ3T3S (ORCPT ); Mon, 30 Oct 2023 15:29:18 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84A3FCC; Mon, 30 Oct 2023 12:29:16 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1698694154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=okhxQnUhQwZrbcdUo7XXc56UihUKqv6O8qJ7nxX4PVE=; b=OvyHHOlBlpoVLw3xBWs9oqxtW+DXUQgwbbHbDbUfNF/MjfJs5bWPOU8I21CIumHlkp0uPz 5ZkiCmUvyIM5ITCYjU15vSbdzkoIOQAnrNLVHdJzkOUfToXjY1WMmUsPke3zwZKHUCO9fI UtYzITvFTF3nlnm+WD5jBWNGfFPpU8AMut0ABL5tfyRWUR/XBuJ0FRwWcdE9BBLsMQjL0r ale9RlO+OeXn67AaYYokAGjJR97Zg4Etah8s4XQzXOtJwRhaOaHgXwoOR0szhF1UpCkx4/ alkoCjUyP5TlAmmgcYuaYzYxYK8j3ZgTEgQwUuli6ov3DrOeN0uTx5PKsH/avw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1698694154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=okhxQnUhQwZrbcdUo7XXc56UihUKqv6O8qJ7nxX4PVE=; b=zFOsaRvRMQAnYrWgBRCI2JmVbPJt7TDD6BVd6QW+l09Vh+xA2ZroG0fVwI53jasucJNFWr /3KnCuuhvsW6sQCQ== To: Sunil V L Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu Subject: Re: [RFC PATCH v2 11/21] PCI: MSI: Add helper function to set system wide MSI support In-Reply-To: References: <20231025202344.581132-1-sunilvl@ventanamicro.com> <20231025202344.581132-12-sunilvl@ventanamicro.com> <87a5s0yyje.ffs@tglx> Date: Mon, 30 Oct 2023 20:29:13 +0100 Message-ID: <874ji7zz7a.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 12:29:35 -0700 (PDT) On Mon, Oct 30 2023 at 23:24, Sunil V. L. wrote: > On Mon, Oct 30, 2023 at 03:28:53PM +0100, Thomas Gleixner wrote: > Just noting related discussion : > https://www.spinics.net/lists/linux-serial/msg57616.html > > The MSI controller on RISC-V (IMSIC) is optional for the platform. So, > when by default pci_msi_enable = 1 and the MSI controller is not > discovered, we get stack trace like below. > So, what I did was, by default call pci_no_msi() to disable MSI and then > call pci_set_msi() to enable when MSI controller is probed. Your taste sensors should have gone out of range ... > But I think Bjorn's suggestion to depend on PCI_BUS_FLAGS_NO_MSI may be > better idea. In that case, we need to set bridge->msi_domain to true in > pci_create_root_bus(). Let me know what do you prefer or if I am > completely missing something here. That's definitely more sensible, but as I said in the other thread, Marc is the one who did the PCI core/bridge setup magic and he is definitely in a better position to answer that bridge->msi_domain question. Thanks, tglx