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Date:   Mon, 30 Oct 2023 19:29:37 -0700
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Subject: Re: [PATCH v2 2/2] dmaengine: idxd: Fix incorrect descriptions for
 GRPCFG register
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To:     'Guanjun' <guanjun@linux.alibaba.com>, <dave.jiang@intel.com>,
        <dmaengine@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <vkoul@kernel.org>, <tony.luck@intel.com>
CC:     <jing.lin@intel.com>, <ashok.raj@intel.com>,
        <sanjay.k.kumar@intel.com>, <megha.dey@intel.com>,
        <jacob.jun.pan@intel.com>, <yi.l.liu@intel.com>,
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References: <20231031022017.1515471-1-guanjun@linux.alibaba.com>
 <20231031022017.1515471-3-guanjun@linux.alibaba.com>
From:   Fenghua Yu <fenghua.yu@intel.com>
In-Reply-To: <20231031022017.1515471-3-guanjun@linux.alibaba.com>
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Hi, Guanjun,

On 10/30/23 19:20, 'Guanjun' wrote:
> From: Guanjun <guanjun@linux.alibaba.com>
> 
> Fix incorrect descriptions for the GRPCFG register which has three
> sub-registers (GRPWQCFG, GRPENGCFG and GRPFLGCFG).
> No functional changes
> 
> Signed-off-by: Guanjun <guanjun@linux.alibaba.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
>   drivers/dma/idxd/registers.h | 13 ++++++++-----
>   1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
> index 7b54a3939ea1..133bd0c170ae 100644
> --- a/drivers/dma/idxd/registers.h
> +++ b/drivers/dma/idxd/registers.h
> @@ -440,12 +440,15 @@ union wqcfg {
>   /*
>    * This macro calculates the offset into the GRPCFG register
>    * idxd - struct idxd *
> - * n - wq id
> - * ofs - the index of the 32b dword for the config register
> + * n - group id
> + * ofs - the index of the 64b qword for the config register
>    *
> - * The WQCFG register block is divided into groups per each wq. The n index
> - * allows us to move to the register group that's for that particular wq.
> - * Each register is 32bits. The ofs gives us the number of register to access.
> + * The GRPCFG register block is divided into three sub-registers, which
> + * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group

s/in each group//

> + * allows us to move to the register group that's for that contains the

s/group/block/

s/that's for//

> + * three sub-registers.
> + * Each register is 64bits. And the ofs in GRPWQCFG gives us the offset

s/Each register/Each register block/

s/GRPWQCFG//

> + * within the GRPCFG register to access.
>    */
>   #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
>   					   (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))

Thanks.

-Fenghua