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Tue, 31 Oct 2023 02:23:06 -0700 (PDT) From: Sergey Khimich To: linux-kernel@vger.kernel.org Cc: Eugeniy Paltsev , Vinod Koul , Philipp Zabel , dmaengine@vger.kernel.org Subject: [PATCH] dmaengine: dw-axi-dmac: Fix inconsistent indenting Date: Tue, 31 Oct 2023 12:23:03 +0300 Message-Id: <20231031092303.129351-1-serghox@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 31 Oct 2023 02:23:19 -0700 (PDT) From: Sergey Khimich Fixed a wrong indentation before axi_dma_iowrite64 in 2 places. | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202310231733.tM3xW1hV-lkp@intel.com/ Fixes: 495e18b16e3d ("dmaengine: dw-axi-dmac: Add support DMAX_NUM_CHANNELS > 16") Signed-off-by: Sergey Khimich --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index f2587159bf5a..723620d0d816 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1236,7 +1236,7 @@ static int dma_chan_pause(struct dma_chan *dchan) val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; } - axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); + axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); } else { if (chan->chip->dw->hdata->reg_map_8_channels) { val = axi_dma_ioread32(chan->chip, DMAC_CHEN); @@ -1283,7 +1283,7 @@ static inline void axi_chan_resume(struct axi_dma_chan *chan) val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT); val |= (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT); } - axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); + axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); } else { if (chan->chip->dw->hdata->reg_map_8_channels) { val = axi_dma_ioread32(chan->chip, DMAC_CHEN); -- 2.30.2