Received: by 2002:a05:7412:f589:b0:e2:908c:2ebd with SMTP id eh9csp183879rdb; Tue, 31 Oct 2023 04:54:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEBVsiv/dpiJr9H64Hxenj5SIlukM451c6wvILveYZvMDe9SE5Ar4CzPyjNaCJGm8dk7u1z X-Received: by 2002:a05:6a20:1387:b0:165:2969:9328 with SMTP id hn7-20020a056a20138700b0016529699328mr8633626pzc.22.1698753292086; Tue, 31 Oct 2023 04:54:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698753292; cv=none; d=google.com; s=arc-20160816; b=hTg5oTz9Iw4gLZPZr8OmgLpgQVO8B5E55t/98Hao2SwTndeIPDRlRqNzyQ6egKghfL tZTVb1UTZcEXdt0FzzRF5QlOqO7SJvlq9I4Bz6kPo5+Xy2JGR6JjVB57Xw7DyqIBtARV chFPdxdGn5r6S3DIJIxHz68/fqhaKVSSnexcZOrzF7fJAe889e//Siw8M76onA9XM4JF p6dRY34MLEpSWtke+J3ufUJb/KBNrKXH7KBp1mAGH1b/inMXWYeFVzFhgYaKdBxSqMj9 QMoj44UKsaR+19BnCVwvioKsjRgX5Iy7y/Vtle8y52OhqR6MUMbGEzfGkN+OcMzJ9yYQ zaMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=Lqr7FKFEj3SUOTv8Qo1rRj+O6M2Sd+0jtfQd0EZsB2Q=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=u8FVUz6X0Uq/u+db01g44Olv/NFMpop3mOQwLlz1fqQ5FKTF2smhgmNnfKpsak9jv7 cig4nCgsZnLObcftTWMNKdbJ79Y8tPEu2gonYAVNT6h1a39Rc4+4AFB0ZfDBKtQ0WdaI fSkICY9LxqwrrRJ72z9U1AzyUPrRU3IegRBKkP4Alxim1rW6lGq0gKq0oG5tgiG6daNh 9CpSzCSEKBRBrZ/n+uG9UQNeRNGbkcsEGmGboTX+2wlnzoHSaTpXWF/ppBa8if4qDei9 aRob7C/CNw3ecpVuFhYvwQDTrskClLrWz0MZRdfYkqoIdCDuPo6fab7veaGlGXxUZ8nj DlCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id x40-20020a056a0018a800b00690d42e3347si908961pfh.157.2023.10.31.04.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 04:54:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D0F9180236E6; Tue, 31 Oct 2023 04:54:50 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235628AbjJaLyr (ORCPT + 99 others); Tue, 31 Oct 2023 07:54:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235341AbjJaLyn (ORCPT ); Tue, 31 Oct 2023 07:54:43 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E834C1; Tue, 31 Oct 2023 04:54:39 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 63F2E8131; Tue, 31 Oct 2023 19:54:37 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 31 Oct 2023 19:54:37 +0800 Received: from ubuntu.localdomain (113.72.146.247) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 31 Oct 2023 19:54:36 +0800 From: Minda Chen To: Conor Dooley , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v10 05/20] PCI: microchip: Rename two PCIe data structures Date: Tue, 31 Oct 2023 19:54:15 +0800 Message-ID: <20231031115430.113586-6-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231031115430.113586-1-minda.chen@starfivetech.com> References: <20231031115430.113586-1-minda.chen@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [113.72.146.247] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 31 Oct 2023 04:54:51 -0700 (PDT) Add PLDA PCIe related data structures by rename data structure name from mc_* to plda_*. axi_base_addr is stayed in struct mc_pcie for it's microchip its own data. The event interrupt codes is still using struct mc_pcie because the event interrupt codes can not be re-used. The modification includes: mc_pcie --> plda_pcie_rp (Get most of data members) mc_msi --> plda_msi Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 96 ++++++++++--------- 1 file changed, 53 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 60870ee1f1c9..3dc4d4ca9d0c 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -22,7 +22,7 @@ #include "pcie-plda.h" /* Number of MSI IRQs */ -#define MC_MAX_NUM_MSI_IRQS 32 +#define PLDA_MAX_NUM_MSI_IRQS 32 /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u @@ -179,25 +179,29 @@ struct event_map { u32 event_bit; }; -struct mc_msi { +struct plda_msi { struct mutex lock; /* Protect used bitmap */ struct irq_domain *msi_domain; struct irq_domain *dev_domain; u32 num_vectors; u64 vector_phy; - DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS); + DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); }; -struct mc_pcie { - void __iomem *axi_base_addr; +struct plda_pcie_rp { struct device *dev; struct irq_domain *intx_domain; struct irq_domain *event_domain; raw_spinlock_t lock; - struct mc_msi msi; + struct plda_msi msi; void __iomem *bridge_addr; }; +struct mc_pcie { + struct plda_pcie_rp plda; + void __iomem *axi_base_addr; +}; + struct cause { const char *sym; const char *str; @@ -313,7 +317,7 @@ static struct mc_pcie *port; static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) { - struct mc_msi *msi = &port->msi; + struct plda_msi *msi = &port->plda.msi; u16 reg; u8 queue_size; @@ -336,10 +340,10 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) static void mc_handle_msi(struct irq_desc *desc) { - struct mc_pcie *port = irq_desc_get_handler_data(desc); + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; - struct mc_msi *msi = &port->msi; + struct plda_msi *msi = &port->msi; void __iomem *bridge_base_addr = port->bridge_addr; unsigned long status; u32 bit; @@ -364,7 +368,7 @@ static void mc_handle_msi(struct irq_desc *desc) static void mc_msi_bottom_irq_ack(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; u32 bitpos = data->hwirq; @@ -373,7 +377,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); phys_addr_t addr = port->msi.vector_phy; msg->address_lo = lower_32_bits(addr); @@ -400,8 +404,8 @@ static struct irq_chip mc_msi_bottom_irq_chip = { static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { - struct mc_pcie *port = domain->host_data; - struct mc_msi *msi = &port->msi; + struct plda_pcie_rp *port = domain->host_data; + struct plda_msi *msi = &port->msi; unsigned long bit; mutex_lock(&msi->lock); @@ -425,8 +429,8 @@ static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *d = irq_domain_get_irq_data(domain, virq); - struct mc_pcie *port = irq_data_get_irq_chip_data(d); - struct mc_msi *msi = &port->msi; + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); + struct plda_msi *msi = &port->msi; mutex_lock(&msi->lock); @@ -456,11 +460,11 @@ static struct msi_domain_info mc_msi_domain_info = { .chip = &mc_msi_irq_chip, }; -static int mc_allocate_msi_domains(struct mc_pcie *port) +static int mc_allocate_msi_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); - struct mc_msi *msi = &port->msi; + struct plda_msi *msi = &port->msi; mutex_init(&port->msi.lock); @@ -484,7 +488,7 @@ static int mc_allocate_msi_domains(struct mc_pcie *port) static void mc_handle_intx(struct irq_desc *desc) { - struct mc_pcie *port = irq_desc_get_handler_data(desc); + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; void __iomem *bridge_base_addr = port->bridge_addr; @@ -511,7 +515,7 @@ static void mc_handle_intx(struct irq_desc *desc) static void mc_ack_intx_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -520,7 +524,7 @@ static void mc_ack_intx_irq(struct irq_data *data) static void mc_mask_intx_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -535,7 +539,7 @@ static void mc_mask_intx_irq(struct irq_data *data) static void mc_unmask_intx_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -625,21 +629,22 @@ static u32 local_events(struct mc_pcie *port) return val; } -static u32 get_events(struct mc_pcie *port) +static u32 get_events(struct plda_pcie_rp *port) { + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 events = 0; - events |= pcie_events(port); - events |= sec_errors(port); - events |= ded_errors(port); - events |= local_events(port); + events |= pcie_events(mc_port); + events |= sec_errors(mc_port); + events |= ded_errors(mc_port); + events |= local_events(mc_port); return events; } static irqreturn_t mc_event_handler(int irq, void *dev_id) { - struct mc_pcie *port = dev_id; + struct plda_pcie_rp *port = dev_id; struct device *dev = port->dev; struct irq_data *data; @@ -655,7 +660,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) static void mc_handle_event(struct irq_desc *desc) { - struct mc_pcie *port = irq_desc_get_handler_data(desc); + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); unsigned long events; u32 bit; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -672,12 +677,13 @@ static void mc_handle_event(struct irq_desc *desc) static void mc_ack_event_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 event = data->hwirq; void __iomem *addr; u32 mask; - addr = port->axi_base_addr + event_descs[event].base + + addr = mc_port->axi_base_addr + event_descs[event].base + event_descs[event].offset; mask = event_descs[event].mask; mask |= event_descs[event].enb_mask; @@ -687,13 +693,14 @@ static void mc_ack_event_irq(struct irq_data *data) static void mc_mask_event_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 event = data->hwirq; void __iomem *addr; u32 mask; u32 val; - addr = port->axi_base_addr + event_descs[event].base + + addr = mc_port->axi_base_addr + event_descs[event].base + event_descs[event].mask_offset; mask = event_descs[event].mask; if (event_descs[event].enb_mask) { @@ -717,13 +724,14 @@ static void mc_mask_event_irq(struct irq_data *data) static void mc_unmask_event_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 event = data->hwirq; void __iomem *addr; u32 mask; u32 val; - addr = port->axi_base_addr + event_descs[event].base + + addr = mc_port->axi_base_addr + event_descs[event].base + event_descs[event].mask_offset; mask = event_descs[event].mask; @@ -811,7 +819,7 @@ static int mc_pcie_init_clks(struct device *dev) return 0; } -static int mc_pcie_init_irq_domains(struct mc_pcie *port) +static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; struct device_node *node = dev->of_node; @@ -889,7 +897,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, } static int mc_pcie_setup_windows(struct platform_device *pdev, - struct mc_pcie *port) + struct plda_pcie_rp *port) { void __iomem *bridge_base_addr = port->bridge_addr; struct pci_host_bridge *bridge = platform_get_drvdata(pdev); @@ -970,7 +978,7 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } -static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port) +static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) { struct device *dev = &pdev->dev; int irq; @@ -1043,12 +1051,12 @@ static int mc_platform_init(struct pci_config_window *cfg) mc_pcie_enable_msi(port, cfg->win); /* Configure non-config space outbound ranges */ - ret = mc_pcie_setup_windows(pdev, port); + ret = mc_pcie_setup_windows(pdev, &port->plda); if (ret) return ret; /* Address translation is up; safe to enable interrupts */ - ret = mc_init_interrupts(pdev, port); + ret = mc_init_interrupts(pdev, &port->plda); if (ret) return ret; @@ -1059,6 +1067,7 @@ static int mc_host_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; void __iomem *bridge_base_addr; + struct plda_pcie_rp *plda; int ret; u32 val; @@ -1066,7 +1075,8 @@ static int mc_host_probe(struct platform_device *pdev) if (!port) return -ENOMEM; - port->dev = dev; + plda = &port->plda; + plda->dev = dev; port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(port->axi_base_addr)) @@ -1075,7 +1085,7 @@ static int mc_host_probe(struct platform_device *pdev) mc_disable_interrupts(port); bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - port->bridge_addr = bridge_base_addr; + plda->bridge_addr = bridge_base_addr; /* Allow enabling MSI by disabling MSI-X */ val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); @@ -1087,10 +1097,10 @@ static int mc_host_probe(struct platform_device *pdev) val &= NUM_MSI_MSGS_MASK; val >>= NUM_MSI_MSGS_SHIFT; - port->msi.num_vectors = 1 << val; + plda->msi.num_vectors = 1 << val; /* Pick vector address from design */ - port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); + plda->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); ret = mc_pcie_init_clks(dev); if (ret) { -- 2.17.1