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Date:   Tue, 31 Oct 2023 16:28:56 +0100
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Md Sadre Alam <quic_mdalam@quicinc.com>
Cc:     agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
        robh+dt@kernel.org, conor+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, richard@nod.at, vigneshr@ti.com,
        broonie@kernel.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
        quic_srichara@quicinc.com, qpic_varada@quicinc.com
Subject: Re: [RFC PATCH 1/5] mtd: nand: ecc-qcom: Add support for ECC Engine
 Driver
Message-ID: <20231031162856.1d9e3246@xps-13>
In-Reply-To: <20231031120307.1600689-2-quic_mdalam@quicinc.com>
References: <20231031120307.1600689-1-quic_mdalam@quicinc.com>
        <20231031120307.1600689-2-quic_mdalam@quicinc.com>
Organization: Bootlin
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Hi,

quic_mdalam@quicinc.com wrote on Tue, 31 Oct 2023 17:33:03 +0530:

Commit log is missing.

> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> Signed-off-by: Sricharan R <quic_srichara@quicinc.com>

If Sricharan is a co developer you need to use the right tags. Please
have a look at the documentation. Using the two SoB here does not mean
anything.

> ---
>  drivers/mtd/nand/Kconfig    |   7 ++
>  drivers/mtd/nand/Makefile   |   1 +
>  drivers/mtd/nand/ecc-qcom.c | 198 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 206 insertions(+)
>  create mode 100644 drivers/mtd/nand/ecc-qcom.c
>=20
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 5b0c2c95f10c..333cec8187c8 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -61,6 +61,13 @@ config MTD_NAND_ECC_MEDIATEK
>  	help
>  	  This enables support for the hardware ECC engine from Mediatek.
> =20
> +config MTD_NAND_ECC_QCOM
> +	tristate "Qualcomm hardware ECC engine"
> +	depends on ARCH_QCOM

Same comment as Mark regarding COMPILE_TEST

> +	select MTD_NAND_ECC
> +	help
> +	  This enables support for the hardware ECC engine from Qualcomm.
> +
>  endmenu
> =20
>  endmenu
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 19e1291ac4d5..c73b8a3456ec 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -3,6 +3,7 @@
>  nandcore-objs :=3D core.o bbt.o
>  obj-$(CONFIG_MTD_NAND_CORE) +=3D nandcore.o
>  obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) +=3D ecc-mtk.o
> +obj-$(CONFIG_MTD_NAND_ECC_QCOM) +=3D ecc-qcom.o qpic_common.o
> =20
>  obj-y	+=3D onenand/
>  obj-y	+=3D raw/
> diff --git a/drivers/mtd/nand/ecc-qcom.c b/drivers/mtd/nand/ecc-qcom.c
> new file mode 100644
> index 000000000000..a85423ed368a
> --- /dev/null
> +++ b/drivers/mtd/nand/ecc-qcom.c
> @@ -0,0 +1,198 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * QCOM ECC Engine  Driver.
> + * Copyright (C) 2023  Qualcomm Inc.
> + * Authors:	Md sadre Alam		<quic_mdalam@quicinc.com>
> + *		Sricharan R		<quic_srichara@quicinc.com>
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/interrupt.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/mutex.h>
> +#include <linux/mtd/nand-qpic-common.h>
> +
> +
> +
> +/* ECC modes supported by the controller */
> +#define ECC_NONE        BIT(0)
> +#define ECC_RS_4BIT     BIT(1)
> +#define ECC_BCH_4BIT    BIT(2)
> +#define ECC_BCH_8BIT    BIT(3)
> +
> +struct qpic_ecc_caps {
> +	u32 err_mask;
> +	u32 err_shift;
> +	const u8 *ecc_strength;
> +	const u32 *ecc_regs;
> +	u8 num_ecc_strength;
> +	u8 ecc_mode_shift;
> +	u32 parity_bits;
> +	int pg_irq_sel;
> +};
> +
> +
> +struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> +{
> +	return container_of(chip, struct qcom_nand_host, chip);
> +}
> +EXPORT_SYMBOL(to_qcom_nand_host);
> +
> +struct qcom_nand_controller *
> +get_qcom_nand_controller(struct nand_chip *chip)
> +{
> +	return container_of(chip->controller, struct qcom_nand_controller,
> +			    controller);
> +}
> +EXPORT_SYMBOL(get_qcom_nand_controller);
> +
> +static struct qpic_ecc *qpic_ecc_get(struct device_node *np)
> +{
> +	struct platform_device *pdev;
> +	struct qpic_ecc *ecc;
> +
> +	pdev =3D of_find_device_by_node(np);
> +	if (!pdev)
> +		return ERR_PTR(-EPROBE_DEFER);
> +
> +	ecc =3D platform_get_drvdata(pdev);
> +	if (!ecc) {
> +		put_device(&pdev->dev);
> +		return ERR_PTR(-EPROBE_DEFER);
> +	}
> +
> +	return ecc;
> +}
> +
> +struct qpic_ecc *of_qpic_ecc_get(struct device_node *of_node)
> +{
> +	struct qpic_ecc *ecc =3D NULL;
> +	struct device_node *np;
> +
> +	np =3D of_parse_phandle(of_node, "nand-ecc-engine", 0);
> +	/* for backward compatibility */

There is no backward compatibility to handle upstream

> +	if (!np)
> +		np =3D of_parse_phandle(of_node, "ecc-engine", 0);
> +	if (np) {
> +		ecc =3D qpic_ecc_get(np);
> +		of_node_put(np);
> +	}
> +
> +	return ecc;
> +}
> +EXPORT_SYMBOL(of_qpic_ecc_get);
> +
> +int qcom_ecc_config(struct qpic_ecc  *ecc, int ecc_strength,
> +			bool wide_bus)
> +{
> +	ecc->ecc_modes =3D (ECC_RS_4BIT | ECC_BCH_8BIT);
> +
> +	if (ecc_strength >=3D 8) {

If your engine does not support more than an 8-bit strength this
condition seems a bit strange.

> +		/* 8 bit ECC defaults to BCH ECC on all platforms */
> +		ecc->bch_enabled =3D true;
> +		ecc->ecc_mode =3D 1;

ecc_modes above, ecc_mode here, not very clear what this is.
Please give meaningful names to your variables, not just the bit name
that this is capturing because here it's unclear what this is.

> +
> +		if (wide_bus) {
> +			ecc->ecc_bytes_hw =3D 14;
> +			ecc->spare_bytes =3D 0;

Spare bytes depend on the flash, you can't use constant values like
that.

I also don't understand what wide_bus is and why it has an impact of
only 1 on the number of ECC bytes. Please make all this more explicit.

> +			ecc->bbm_size =3D 2;
> +		} else {
> +			ecc->ecc_bytes_hw =3D 13;
> +			ecc->spare_bytes =3D 2;
> +			ecc->bbm_size =3D 1;
> +		}
> +	} else {
> +		/*
> +		 * if the controller supports BCH for 4 bit ECC, the controller
> +		 * uses lesser bytes for ECC. If RS is used, the ECC bytes is
> +		 * always 10 bytes
> +		 */
> +		if (ecc->ecc_modes & ECC_BCH_4BIT) {
> +			/* BCH */
> +			ecc->bch_enabled =3D true;
> +			ecc->ecc_mode =3D 0;
> +			if (wide_bus) {
> +				ecc->ecc_bytes_hw =3D 8;
> +				ecc->spare_bytes =3D 2;
> +				ecc->bbm_size =3D 2;
> +			} else {
> +				ecc->ecc_bytes_hw =3D 7;
> +				ecc->spare_bytes =3D 4;
> +				ecc->bbm_size =3D 1;
> +			}
> +		} else {
> +			/* RS */
> +			ecc->ecc_bytes_hw =3D 10;
> +			if (wide_bus) {
> +				ecc->spare_bytes =3D 0;
> +				ecc->bbm_size =3D 2;
> +			} else {
> +				ecc->spare_bytes =3D 1;
> +				ecc->bbm_size =3D 1;
> +			}
> +		}
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(qcom_ecc_config);

Thanks,
Miqu=C3=A8l