Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3;
From:   Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
To:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc:     Aleksandar Rikalo <arikalo@gmail.com>,
        Chao-ying Fu <cfu@wavecomp.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>,
        Geert Uytterhoeven <geert@linux-m68k.org>,
        Greg Ungerer <gerg@kernel.org>,
        Hauke Mehrtens <hauke@hauke-m.de>,
        Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
        Marc Zyngier <maz@kernel.org>,
        Paul Burton <paulburton@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Serge Semin <fancer.lancer@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Tiezhu Yang <yangtiezhu@loongson.cn>
Subject: [PATCH v3 03/11] irqchip: mips-gic: Introduce for_each_online_cpu_gic()
Date:   Tue, 31 Oct 2023 17:49:19 +0100
Message-Id: <20231031164927.371663-4-aleksandar.rikalo@syrmia.com>
In-Reply-To: <20231031164927.371663-1-aleksandar.rikalo@syrmia.com>
References: <20231031164927.371663-1-aleksandar.rikalo@syrmia.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?y8r+B4Res9tRcGHWGhN/env3YcGyqMLvmsuLzUCSbR5S4avvzJlwQ8uwYIiz?=
 =?us-ascii?Q?g7bu2acuKaYbOINZTDiId26XdX1qzExlJhvop3qHzkd5NBlzxAUEUM7V1zfK?=
 =?us-ascii?Q?k/dC/+YXnbjGfI5ISIc7ulZilWqjWRteHH5y58JoGh7NB7pQF4PLghPZ8Qpl?=
 =?us-ascii?Q?GRmWz0jYhQWUebnTJY9NeOenoC6Vpos5K61jCK8SLOYWqXLfHUqFBJV5oIUY?=
 =?us-ascii?Q?75QcyHVQU66e1u0/4vVkNbsJP8j4lq7++O2ADwxNbTHzT4LfnhnD90uJQVRH?=
 =?us-ascii?Q?+IK9PZ/Ca02HR60sBsBlM0+WoUt7IaeZSt1ahGtD0JVlDEajV5xQqpTT7FQD?=
 =?us-ascii?Q?xNg0F9vWxd2hPzCeSylFe6uxpVaW07Tk/PQYY5VfFgyCZOKbmOQO5Y1DBq8U?=
 =?us-ascii?Q?lTDBtGDswxEHoIEi8STZedJKlWe3kPiao6NTAq3WgC0/OCacMwta80rosx6h?=
 =?us-ascii?Q?0wNQ1sIrG2yiTzEdDIJQR8kqpmh+EYRr2ar4e0uHFvtMETxbCtO1WJciaUKx?=
 =?us-ascii?Q?kd3kAFgZUJUTk8zavV/5sG8bzKAYrc/phL7Cvvw0IKoWrVaDE1+sNFvQxIpn?=
 =?us-ascii?Q?pnt80L/cy8NTI0FLp9roQoSTa8CeQTzJgB/aKbwWL5Uy10bXAQXHpxG78Xq/?=
 =?us-ascii?Q?pzhVl4cYy1dGdIN9NMZFEad5osQJgNsjNYBLlHsQCrhz6OE4QTnsr80vyjHL?=
 =?us-ascii?Q?DME3rhnsDDEWlhUbah/BZxc2RCs5OrfWJF8fm6z8LFpG5IgCdYjiXylaQQPX?=
 =?us-ascii?Q?2ZcMQPx75WzqhDMFhttGbg3wyE5L/nq9ChZbyseLxeC8/86WaNlJus62e6Dh?=
 =?us-ascii?Q?E1dFl7BdN0SO6dniWBPRzgYGD0Zv22NNzSVv3SUeIr9vRwkoH6G6n5jlzsBW?=
 =?us-ascii?Q?ab71Jwj1qHZbqs7kmoKUSFqhC98IjzGVJx2Jqafmc5mNBEDMwFZskd0BR11H?=
 =?us-ascii?Q?s6xaJ0nIt+n/f+s+CWDq48RnYMA7Of7R9TNT7eOs52wQCQKh6sBvrOarQy6F?=
 =?us-ascii?Q?MBzCa0V9DL2mQcV4iRJy+tl5ljnqrG47ShhQVkTx+X0N8DTevbB8rbdA/PEN?=
 =?us-ascii?Q?XUuJh+EbXUVukdVWik1JcYOuCNgDMDrb1KkuvvI47w+13Q1BgNQMbIu+1IbZ?=
 =?us-ascii?Q?nhpSbPWsFaTkS4PtAUcr95blQEY5Zh/4o2el/5FF6RadJpynYLHpgufjB+3c?=
 =?us-ascii?Q?g12Bzqvf/ga/SNnHWLSNvGP9HGtv7cp5CSoPjZ/SCIHllQtG6mUzQgp/AIWg?=
 =?us-ascii?Q?fEcMeeqmTmbrP3wbNQivz96s0YM0k9qqMWV0HJ1uZv+Up2wjuL5tJkocpBts?=
 =?us-ascii?Q?1Zu7F90PDKlW566bGEMF9u9Nx2vvAFiFV4y1wfKdrujNGIsqFhdSTY37DGfQ?=
 =?us-ascii?Q?7kLnf3f5ndzXnsOK4TCp9w1jA7KDchuHtMlxMBjo4MuZTWTWWsFUJiIK7U4T?=
 =?us-ascii?Q?JTogCs+9XASAm9qXQfiBv0WRkL3WXfwlKDF4wzBSBpgJ2Kw1x+7e0pjwIB+F?=
 =?us-ascii?Q?JLxw8vSiHMHr9ECDWTh7r213Y7wrNNJUKtwhK89G80nlZQEm0xOUxZiLJ+7U?=
 =?us-ascii?Q?66Vj9RfauyLleyS5DfC4d0GQwa+/b+7UBzhZYXc808g42XCib7iPV69bV8dA?=
 =?us-ascii?Q?8Q=3D=3D?=
X-OriginatorOrg: syrmia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: ac47c71d-db40-4c4a-4eec-08dbda3160ae
X-MS-Exchange-CrossTenant-AuthSource: VI1PR0302MB3486.eurprd03.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2023 16:49:41.4592
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 19214a73-c1ab-4e19-8f59-14bdcb09a66e
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: HoqN+gM0JP0Ia3LhJA31cSyc7BX5hdRY0omzCeS5j/Mkc+OCeaDi2xrGgZwJah/xK8U0FcZBxaTjAXtCP8aIU8o/ZFNe5FrDDg0DcqMHrdw=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7187
X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID,
	DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,
	SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable
	autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 31 Oct 2023 09:53:08 -0700 (PDT)

From: Paul Burton <paulburton@kernel.org>

A few pieces of code in the MIPS GIC driver operate on the GIC local
register block for each online CPU, accessing each via the GIC's
other/redirect register block. This patch abstracts the process of
iterating over online CPUs & configuring the other/redirect region to
access their registers through a new for_each_online_cpu_gic() macro.

This simplifies users of the new macro slightly, and more importantly
prepares us for handling multi-cluster systems where the register
configuration will be done via the CM's GCR_CL_REDIRECT register. By
abstracting all other/redirect block configuration through this macro,
and the __gic_with_next_online_cpu() function which backs it, users will
trivially gain support for multi-cluster when it is implemented in
__gic_with_next_online_cpu().

Signed-off-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
---
 drivers/irqchip/irq-mips-gic.c | 61 +++++++++++++++++++++++++++++-----
 1 file changed, 52 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 76253e864f23..9e7182150b5c 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -66,6 +66,52 @@ static struct gic_all_vpes_chip_data {
 	bool	mask;
 } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
 
+static int __gic_with_next_online_cpu(int prev)
+{
+	unsigned int cpu;
+
+	/* Discover the next online CPU */
+	cpu = cpumask_next(prev, cpu_online_mask);
+
+	/* If there isn't one, we're done */
+	if (cpu >= nr_cpu_ids)
+		return cpu;
+
+	/*
+	 * Lock access to the next CPU's GIC local register block.
+	 *
+	 * In the single cluster case we simply set GIC_VL_OTHER. The caller
+	 * holds gic_lock so nothing can clobber the value we write.
+	 */
+	write_gic_vl_other(mips_cm_vp_id(cpu));
+
+	return cpu;
+}
+
+static inline void __lockdep_assert_held(raw_spinlock_t *gic_lock)
+{
+	lockdep_assert_held(gic_lock);
+}
+
+/**
+ * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
+ * @cpu: An integer variable to hold the current CPU number
+ * @gic_lock: A pointer to raw spin lock used as a guard
+ *
+ * Iterate over online CPUs & configure the other/redirect register region to
+ * access each CPUs GIC local register block, which can be accessed from the
+ * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or
+ * their derivatives.
+ *
+ * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER
+ * cannot be clobbered.
+ */
+#define for_each_online_cpu_gic(cpu, gic_lock)		\
+	for (__lockdep_assert_held(gic_lock),		\
+	     (cpu) = __gic_with_next_online_cpu(-1);	\
+	     (cpu) = __gic_with_next_online_cpu(cpu),	\
+	     (cpu) < nr_cpu_ids;)
+
 static void gic_clear_pcpu_masks(unsigned int intr)
 {
 	unsigned int i;
@@ -358,10 +404,9 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 	cd->mask = false;
 
 	raw_spin_lock_irqsave(&gic_lock, flags);
-	for_each_online_cpu(cpu) {
-		write_gic_vl_other(mips_cm_vp_id(cpu));
+	for_each_online_cpu_gic(cpu, &gic_lock)
 		write_gic_vo_rmask(BIT(intr));
-	}
+
 	raw_spin_unlock_irqrestore(&gic_lock, flags);
 }
 
@@ -376,10 +421,9 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 	cd->mask = true;
 
 	raw_spin_lock_irqsave(&gic_lock, flags);
-	for_each_online_cpu(cpu) {
-		write_gic_vl_other(mips_cm_vp_id(cpu));
+	for_each_online_cpu_gic(cpu, &gic_lock)
 		write_gic_vo_smask(BIT(intr));
-	}
+
 	raw_spin_unlock_irqrestore(&gic_lock, flags);
 }
 
@@ -534,10 +578,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 		return -EPERM;
 
 	raw_spin_lock_irqsave(&gic_lock, flags);
-	for_each_online_cpu(cpu) {
-		write_gic_vl_other(mips_cm_vp_id(cpu));
+	for_each_online_cpu_gic(cpu, &gic_lock)
 		write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
-	}
+
 	raw_spin_unlock_irqrestore(&gic_lock, flags);
 
 	return 0;
-- 
2.25.1