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Message-ID: <65cc630c-1d71-48e1-b639-b92221a8d7b1@gmail.com>
Date:   Tue, 31 Oct 2023 20:46:42 +0100
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Subject: Re: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
To:     Mantas Pucka <mantas@8devices.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Bhupesh Sharma <bhupesh.sharma@linaro.org>
Cc:     Abhishek Sahu <absahu@codeaurora.org>,
        Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org>,
        Sricharan R <sricharan@codeaurora.org>,
        Sivaprakash Murugesan <sivaprak@codeaurora.org>,
        linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
        linux-clk@vger.kernel.org
References: <1682338412-15420-1-git-send-email-mantas@8devices.com>
 <1682338412-15420-3-git-send-email-mantas@8devices.com>
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From:   Robert Marko <robimarko@gmail.com>
In-Reply-To: <1682338412-15420-3-git-send-email-mantas@8devices.com>
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On 24. 04. 2023. 14:13, Mantas Pucka wrote:
> IPQ6018 has one SD/eMMC controller, add node for it.
>
> Signed-off-by: Mantas Pucka <mantas@8devices.com>

Tested-by: Robert Marko <robimarko@gmail.com>

> ---
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 9ff4e9d45065..b129b23d68b1 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -414,6 +414,29 @@
>   			};
>   		};
>   
> +		sdhc_1: mmc@7804000 {
> +			compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
> +			reg = <0x0 0x07804000 0x0 0x1000>,
> +			      <0x0 0x07805000 0x0 0x1000>,
> +			      <0x0 0x07808000 0x0 0x2000>;
> +			reg-names = "hc", "cqhci", "ice";
> +
> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> +				 <&gcc GCC_SDCC1_APPS_CLK>,
> +				 <&xo>,
> +				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> +			clock-names = "iface", "core", "xo", "ice";
> +
> +			resets = <&gcc GCC_SDCC1_BCR>;
> +			supports-cqe;
> +			bus-width = <8>;
> +			status = "disabled";
> +		};
> +
>   		blsp_dma: dma-controller@7884000 {
>   			compatible = "qcom,bam-v1.7.0";
>   			reg = <0x0 0x07884000 0x0 0x2b000>;