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[23.128.96.36]) by mx.google.com with ESMTPS id nn8-20020a17090b38c800b00277651787f1si1636927pjb.145.2023.10.31.15.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 15:06:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Mdtfh7xQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id EAA568065CAA; Tue, 31 Oct 2023 15:05:55 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344874AbjJaWFs (ORCPT + 99 others); Tue, 31 Oct 2023 18:05:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229621AbjJaWFq (ORCPT ); Tue, 31 Oct 2023 18:05:46 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D115EA for ; Tue, 31 Oct 2023 15:05:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698789944; x=1730325944; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=IwpVz6MF9Gm8aHgWudjf+PhbOFRizyKxWaZV8j9bj5E=; b=Mdtfh7xQZFWl3kjvRWGxNaRUXoj0eiRTfclxrBil5+/boL/OQPW4+17O rCXhVWPQ34QyEkLArNPDAMTDvKY2XmpsUXDy2/vtmiB33kybn1OEbI/jf 1JP/F6/7UAyta+6tY+H4nv2WCWJoa8oNU52HAj03+wHc89vEyda222Yq/ pKXtbVVTB2TjV7hw+cHfczYat0EMyhqjnuKT9/t7d6uxwBTNPqSwCAggx kwJC4LAkJnMP/KgiDZaOyAhbPg1QhwCyWcmTfTcyUWktzvEhirhMsNxmN hSHfdmqyywv+d26EdVmJptUINUFIiE9plswALXsvhFpD/nr2YobVLcoF5 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10880"; a="391251400" X-IronPort-AV: E=Sophos;i="6.03,266,1694761200"; d="scan'208";a="391251400" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 15:05:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,266,1694761200"; d="scan'208";a="8456911" Received: from agluck-desk3.sc.intel.com ([172.25.222.74]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 15:05:43 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Peter Newman , x86@kernel.org Cc: Shaopeng Tan , James Morse , Jamie Iles , Babu Moger , Randy Dunlap , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH] x86/resctrl: Fix unused variable warning in cache_alloc_hsw_probe() Date: Tue, 31 Oct 2023 15:05:34 -0700 Message-ID: <20231031220534.37730-1-tony.luck@intel.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 31 Oct 2023 15:05:56 -0700 (PDT) In a "W=1" build gcc throws a warning: arch/x86/kernel/cpu/resctrl/core.c: In function ‘cache_alloc_hsw_probe’: arch/x86/kernel/cpu/resctrl/core.c:139:16: warning: variable ‘h’ set but not used Fix by switching from rdmsr() to rdmsrl() using a single u64 argument for the MSR value instead of the pair of u32 for the high and low halves. Signed-off-by: Tony Luck --- This has been annoying me for a while as the only warning from the resctrl code when building with W=1. N.B. compile tested only. I don't have a Haswell system to check this works. arch/x86/kernel/cpu/resctrl/core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 19e0681f0435..4084131d391d 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -136,15 +136,16 @@ static inline void cache_alloc_hsw_probe(void) { struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; struct rdt_resource *r = &hw_res->r_resctrl; - u32 l, h, max_cbm = BIT_MASK(20) - 1; + u32 max_cbm = BIT_MASK(20) - 1; + u64 l3_cbm_0; if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) return; - rdmsr(MSR_IA32_L3_CBM_BASE, l, h); + rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0); /* If all the bits were set in MSR, return success */ - if (l != max_cbm) + if (l3_cbm_0 != max_cbm) return; hw_res->num_closid = 4; -- 2.41.0