Received: by 2002:a05:7412:f589:b0:e2:908c:2ebd with SMTP id eh9csp660937rdb; Tue, 31 Oct 2023 20:32:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHsITMVosq42frH+FDXd0gzD4RF4FxBo2s8rYOj/jGL5iDpiVCYmRhyxf6jxT2zJ5Sh1EOI X-Received: by 2002:a17:90a:fe95:b0:27c:ecec:8854 with SMTP id co21-20020a17090afe9500b0027cecec8854mr6280131pjb.7.1698809545116; Tue, 31 Oct 2023 20:32:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698809545; cv=none; d=google.com; s=arc-20160816; b=dLecgt4pkeakqnPg+TqEIq5n1O3zEPIa3juKB7HdDIwH9S08fmks64mJuUSCs8B7WD o2krBPvV2UKRkSmvDaletzWRzDYQpo53Ti+kVxL7wMf+Q9gnf22HoEA8hnMdcnZ/9FVs rX6V7N30x0iPmRioXsQZPkQNDHsDa59jegO7p+efPXDiA+Q91lljtxhr4KwErjeDV1uk cy6l42TV68vdAV4JuuLbu1chJV6NZBzpe4xZKseRYDOEK3USl9QDHyj6McCwTwbnV8pE vZTe26rLyCdP3/GzM3X/bOCsO3V4zMyrcFImQmu4S8kOAICqWhrlePSf0ljnJIemmiwx iApA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id:dkim-signature; bh=z0KpbqEoDMMjRpM6kkxuRlzzdElVJuz53E15w9FSfoA=; fh=VAeDoVGJHd/itJUO43QS3s3596km6tLyA8r9/kqCa9g=; b=A/5EnJYvKI62EkhBfDRzx6STd1lpB11PLG5WbyjgIUfLma/kN8h2r8vRG6v5gO9ZZO +A62CBaQkait/CMkCNGGeqjgxco9UqiKG5KL088GJ2L9rTgVv8nzuYt8SNRHWjZv87CP wkBvsTGtCkEw3GO0fPT845Cizo4+d5T3XwzLeya54++gCRYoehNqRnY9kpZENfFMCyej Kovqod6mwDuQth7cKz0C2XIeGkjBj7HwUSlnwe1mmlAn0xXqq7ZVKWO0RLKkKY8gv/Uf aV+TfnacxS7xysRdoHcS04+MXQdVj0SevMt4rrTHymYfBR2Xw6u+EMt4Bg9bbEwMpg9t ohLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KZ904NB9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id fz21-20020a17090b025500b0027d1b42875bsi2030296pjb.64.2023.10.31.20.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 20:32:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KZ904NB9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 0B2058084964; Tue, 31 Oct 2023 20:32:18 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232398AbjKADcB (ORCPT + 99 others); Tue, 31 Oct 2023 23:32:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231924AbjKADb7 (ORCPT ); Tue, 31 Oct 2023 23:31:59 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58579A4; Tue, 31 Oct 2023 20:31:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698809513; x=1730345513; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=QqGO01Y/1oyO0lTK3Mc38r00JIyBFbJFCspKsxa3IGY=; b=KZ904NB9XEtOynIz4iTCx+dpROpak2q49nBciEcHCuvWmKgORlYsolLy B+Wmx9nVw2VxvNq0BWpm1+FJebPFpXo+khljRadonWz9AzLX5iksxmgbb 4hTOMpMm/XSkV9izCM1vMceVsfiINhEV09u+oID4P8ZK3vnNDrLW2Y4qa B57vBHSlKqBykP59NNgsMaLchMmDGHh6lKHGJ9VXKUgdl+VzII0KRG9sV kiI81x0u7mGXZiq75+TAWwpuPX6MmT8m0vmj5vFTPqPUyyEoKMorDTQRD 6DOVddKSoWRkmVMzzspBCda+gbTUVF1ERyO8aHdPMTA9zAl+JDw1NKFWn Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10880"; a="474668040" X-IronPort-AV: E=Sophos;i="6.03,267,1694761200"; d="scan'208";a="474668040" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 20:31:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10880"; a="934316919" X-IronPort-AV: E=Sophos;i="6.03,267,1694761200"; d="scan'208";a="934316919" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.93.12.33]) ([10.93.12.33]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2023 20:31:49 -0700 Message-ID: Date: Wed, 1 Nov 2023 11:31:46 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Patch 1/2] KVM: x86/pmu: Add Intel CPUID-hinted TopDown slots event Content-Language: en-US To: Jim Mattson Cc: Sean Christopherson , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Dapeng Mi , Like Xu , Kan Liang References: <20231031090613.2872700-1-dapeng1.mi@linux.intel.com> <20231031090613.2872700-2-dapeng1.mi@linux.intel.com> From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 31 Oct 2023 20:32:18 -0700 (PDT) On 11/1/2023 11:04 AM, Jim Mattson wrote: > On Tue, Oct 31, 2023 at 6:59 PM Mi, Dapeng wrote: >> On 11/1/2023 2:22 AM, Jim Mattson wrote: >>> On Tue, Oct 31, 2023 at 1:58 AM Dapeng Mi wrote: >>>> This patch adds support for the architectural topdown slots event which >>>> is hinted by CPUID.0AH.EBX. >>> Can't a guest already program an event selector to count event select >>> 0xa4, unit mask 1, unless the event is prohibited by >>> KVM_SET_PMU_EVENT_FILTER? >> Actually defining this new slots arch event is to do the sanity check >> for supported arch-events which is enumerated by CPUID.0AH.EBX. >> Currently vPMU would check if the arch event from guest is supported by >> KVM. If not, it would be rejected just like intel_hw_event_available() >> shows. >> >> If we don't add the slots event in the intel_arch_events[] array, guest >> may program the slots event and pass the sanity check of KVM on a >> platform which actually doesn't support slots event and program the >> event on a real GP counter and got an invalid count. This is not correct. > On physical hardware, it is possible to program a GP counter with the > event selector and unit mask of the slots event whether or not the > platform supports it. Isn't KVM wrong to disallow something that a > physical CPU allows? Yeah, I agree. But I'm not sure if this is a flaw on PMU driver. If an event is not supported by the hardware,  we can't predict the PMU's behavior and a meaningless count may be returned and this could mislead the user. Add Kan to confirm this. Hi Kan, Have you any comments on this? Thanks. > >>> AFAICT, this change just enables event filtering based on >>> CPUID.0AH:EBX[bit 7] (though it's not clear to me why two independent >>> mechanisms are necessary for event filtering). >> >> IMO, these are two different things. this change is just to enable the >> supported arch events check for slot events, the event filtering is >> another thing. > How is clearing CPUID.0AH:EBX[bit 7] any different from putting {event > select 0xa4, unit mask 1} in a deny list with the PMU event filter? I think there is no difference in the conclusion but with two different methods.