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Wed, 01 Nov 2023 06:29:25 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A16TOJh023479 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 1 Nov 2023 06:29:24 GMT Received: from [10.239.133.211] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 31 Oct 2023 23:29:20 -0700 Message-ID: <15cbd29f-100c-48cc-9fc6-fde222a783b1@quicinc.com> Date: Wed, 1 Nov 2023 14:29:17 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/8] dt-bindings: arm: Add support for CMB element size To: Rob Herring CC: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Konrad Dybcio , Mike Leach , Krzysztof Kozlowski , Jinlong Mao , Leo Yan , Greg Kroah-Hartman , , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Song Chai , , References: <1698202408-14608-1-git-send-email-quic_taozha@quicinc.com> <1698202408-14608-2-git-send-email-quic_taozha@quicinc.com> <20231026212546.GA420866-robh@kernel.org> Content-Language: en-US From: Tao Zhang In-Reply-To: <20231026212546.GA420866-robh@kernel.org> Content-Type: text/plain; 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Tue, 31 Oct 2023 23:30:09 -0700 (PDT) On 10/27/2023 5:25 AM, Rob Herring wrote: > On Wed, Oct 25, 2023 at 10:53:21AM +0800, Tao Zhang wrote: >> Add property "qcom,cmb-elem-size" to support CMB(Continuous >> Multi-Bit) element for TPDM. The associated aggregator will read >> this size before it is enabled. CMB element size currently only >> supports 32-bit and 64-bit. >> >> Signed-off-by: Tao Zhang >> Signed-off-by: Mao Jinlong >> --- >> .../bindings/arm/qcom,coresight-tpdm.yaml | 27 ++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> index 61ddc3b..f9a2025 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> @@ -52,6 +52,14 @@ properties: >> $ref: /schemas/types.yaml#/definitions/uint8 >> enum: [32, 64] >> >> + qcom,cmb-element-size: > What are the units? Use '-bits' suffix. Yes, its unit should be bit. Do you mean that you prefer to use "qcom, cmb-element-size-bits"? Do I also need to replace "qcom, dsb-element-size" with "qcom, dsb-element-size-bits". > >> + description: >> + Specifies the CMB(Continuous Multi-Bit) element size supported by >> + the monitor. The associated aggregator will read this size before it >> + is enabled. CMB element size currently only supports 32-bit and 64-bit. > The enum says 8-bit is supported. Yes, 8-bit is supported. I will update the description in the next patch series. Best, Tao > >> + $ref: /schemas/types.yaml#/definitions/uint8 >> + enum: [8, 32, 64] >> + >> qcom,dsb-msrs-num: >> description: >> Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) >> @@ -110,4 +118,23 @@ examples: >> }; >> }; >> >> + tpdm@6c29000 { >> + compatible = "qcom,coresight-tpdm", "arm,primecell"; >> + reg = <0x06c29000 0x1000>; >> + reg-names = "tpdm-base"; >> + >> + qcom,cmb-element-size = /bits/ 8 <64>; >> + >> + clocks = <&aoss_qmp>; >> + clock-names = "apb_pclk"; >> + >> + out-ports { >> + port { >> + tpdm_ipcc_out_funnel_center: endpoint { >> + remote-endpoint = >> + <&funnel_center_in_tpdm_ipcc>; >> + }; >> + }; >> + }; >> + }; >> ... >> -- >> 2.7.4 >>