Received: by 2002:a05:7412:f589:b0:e2:908c:2ebd with SMTP id eh9csp1199396rdb; Wed, 1 Nov 2023 14:29:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHXtn0PiqqC3lsAfBbKbgoKxWOM/asKsd9BiJiXMAUx4Ea3wJ8WR0EjRcG93fWiFrWPUWbv X-Received: by 2002:a05:6a21:7802:b0:181:19ef:4ff0 with SMTP id be2-20020a056a21780200b0018119ef4ff0mr4839227pzc.35.1698874190817; Wed, 01 Nov 2023 14:29:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698874190; cv=none; d=google.com; s=arc-20160816; b=tgpt8NT6KzQfDqx2uQw8aOIG6YFWBo0D1PEPvFaZl5CmAeuweykqw47bCE6DFTlSPw R4sWfPKgcsz61Uf3Uh+OqmqfcOoCzdFjdxoJUGshs5gOVGC4yEFWDHGDvHX7MIXGJ3Lo NfUj8D5vkvbzM6vmLfi2CK8QDV0PYu0a2pD5mKxH0BE0xnI03UBtEGocZpgFsxK6QQot 4umT5/r4vijzVPu9YfTIkD4ntednsglkWZIk8Qxz6iVhZqIIimUJrQwxJyo1eyBzScD6 YTBCYu4ptd45n5WfKCBIkux8PPczCB9ms5a9K1U/VYNJYwWIZltNAOAWVp3eQBeZNnZJ gKLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=Oecjfdn9qXi32jEmitsKgnhqeMKJivxOJDI7gWIxsLQ=; fh=w7CgwB2ga/dncEUdB8aMAYYYwfN5tMLryEoUWnbarCA=; b=F9xN9guTA9cm7V4YHnVmNfkkwHWPMFXy/97vDEApTx4M6sG5UhXBw2IIvI31qOamfJ QotUT76mxh9DRwQpqSDJB10XiinlmQBw2J9Kr4eNi6qI2uazAo0zEkDDd982ZmjdkocG 8MAeut+lQdOCCdmNB76KGuJ1FRuAKgbscWosmCKVqW4VckyN9Z3KROzB3duR+P9VBDtW dcIL2oxIP1KqOSTH6wseGqIRG+qmtqOz4ftggfMt3lwqSqCypmXtqi6gPl7BMFAscMzZ k5uc8sSVfGhWdJY7sDqvCZM61SL8qHS4Nk0R+YrosgannSxmlLW8489OEE12JxqQk0l7 IL0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VvVxEBRW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id p29-20020a63741d000000b005b8f9dbbd5fsi610151pgc.409.2023.11.01.14.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 14:29:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VvVxEBRW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 3FFCF8082DEE; Wed, 1 Nov 2023 14:29:44 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345467AbjKAV3L (ORCPT + 99 others); Wed, 1 Nov 2023 17:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345342AbjKAV3K (ORCPT ); Wed, 1 Nov 2023 17:29:10 -0400 Received: from mail-yw1-x1136.google.com (mail-yw1-x1136.google.com [IPv6:2607:f8b0:4864:20::1136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCE61115 for ; Wed, 1 Nov 2023 14:29:04 -0700 (PDT) Received: by mail-yw1-x1136.google.com with SMTP id 00721157ae682-5b31c5143a0so3509567b3.3 for ; Wed, 01 Nov 2023 14:29:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698874144; x=1699478944; darn=vger.kernel.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Oecjfdn9qXi32jEmitsKgnhqeMKJivxOJDI7gWIxsLQ=; b=VvVxEBRWw46bR55cGJJNWQBmjfn+z3gVkhxevtkc0BK6qAEOgXR0VjZJ9ek8n1h1Y0 Xv2eXSxMpnCVOEGBCZ3cGGDKihQYCmZOHDyIllFHf7OlGw9Gx3uYVb7ERwn7SaNxF12f I/Bx62mywGvdP15AzrlqK5nyTYMX5yrCMYLwBNB6z5cIAgOKCJJWU39K5kApfcdctgGv M9ghsaPN5uLi8hvUTXk80u+S4Fe8V7ntplTBb2pDxcbzU+w7ueSfGMHWi8LwjJ78zxZd 58qW7HI265MipW/nHjo7Bovl4rGNiSgQAPEifp0TcXFryaKLMlahLVxkNBmf7g59YLqk wKVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698874144; x=1699478944; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Oecjfdn9qXi32jEmitsKgnhqeMKJivxOJDI7gWIxsLQ=; b=hmKTc6b5VLpPejFMwu5sQ7OWSWP2FYfTthAp1neDtqjFn0+UlOcuOT+9p7WmFLfT/d JADoxsFp5wd6M+7kTp+rqk+0RsXhGXZLGq8Ean0qzi6cdwTFmLd5xR8DNR7ggznNBucf 3b3K6+yfF9z5pSqHWE6jUqp/wIWxP0DyMrG7gGqzVvE0rlnjBgBxwCenma1bGF2aYOLc Rt7RcEE55RcUopUUfsnj1N9YwGr8piyOp255xbR8AihxR5ivDGy+nCtm53/z5f8qqtrL gygYDJUdrUzNVjwHzyKM26Zwt7Rr/jLFwzxyZgEpPbqT8m6pDrfL5GqCRzaukgH4CIHX JEMg== X-Gm-Message-State: AOJu0YxvXqTWytTf7MKTkQrLIOzYaYDWXZ0zb5i7juytzErxh3yLHccx 1Jf43L5PDX8HOYqW1D/rXZqjliLAB3R/J1mXuKarsg== X-Received: by 2002:a81:d308:0:b0:5a8:60ad:39a4 with SMTP id y8-20020a81d308000000b005a860ad39a4mr16560750ywi.3.1698874143732; Wed, 01 Nov 2023 14:29:03 -0700 (PDT) MIME-Version: 1.0 References: <20231101-gdsc-hwctrl-v3-0-0740ae6b2b04@linaro.org> <20231101-gdsc-hwctrl-v3-3-0740ae6b2b04@linaro.org> In-Reply-To: <20231101-gdsc-hwctrl-v3-3-0740ae6b2b04@linaro.org> From: Dmitry Baryshkov Date: Wed, 1 Nov 2023 23:28:52 +0200 Message-ID: Subject: Re: [PATCH RESEND v3 3/5] clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode To: Abel Vesa Cc: "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Pavel Machek , Len Brown , Greg Kroah-Hartman , Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Taniya Das , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-media@vger.kernel.org, Jagadeesh Kona Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 01 Nov 2023 14:29:44 -0700 (PDT) On Wed, 1 Nov 2023 at 11:06, Abel Vesa wrote: > > From: Jagadeesh Kona > > Add support for set and get hwmode callbacks to switch the GDSC between > SW and HW modes. Currently, the GDSC is moved to HW control mode > using HW_CTRL flag and if this flag is present, GDSC is moved to HW > mode as part of GDSC enable itself. The intention is to keep the > HW_CTRL flag functionality as is, since many older chipsets still use > this flag. > > Introduce a new HW_CTRL_TRIGGER flag to switch the GDSC back and forth > between HW/SW modes dynamically at runtime. If HW_CTRL_TRIGGER flag is > present, register set_hwmode_dev callback to switch the GDSC mode which > can be invoked from consumer drivers using dev_pm_genpd_set_hwmode > function. Unlike HW_CTRL flag, HW_CTRL_TRIGGER won't move the GDSC to HW > control mode as part of GDSC enable itself, GDSC will be moved to HW > control mode only when consumer driver explicity calls > dev_pm_genpd_set_hwmode to switch to HW mode. Also add the > dev_pm_genpd_get_hwmode to allow the consumers to read the actual > HW/SW mode from hardware. Can we add two new flags: - HW_CTRL_TRIGGER - DEFAULT_HW_TRIGGER And then define HW_CTRL as HW_CTRL_TRIGGER | DEFAULT_HW_TRIGGER ? This way older platforms will keep existing behaviour, but can gradually migrate to the new callbacks? > > Signed-off-by: Jagadeesh Kona > Signed-off-by: Abel Vesa > --- > drivers/clk/qcom/gdsc.c | 32 ++++++++++++++++++++++++++++++++ > drivers/clk/qcom/gdsc.h | 1 + > 2 files changed, 33 insertions(+) > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index 5358e28122ab..c763524cd5da 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -363,6 +363,34 @@ static int gdsc_disable(struct generic_pm_domain *domain) > return 0; > } > > +static int gdsc_set_hwmode(struct generic_pm_domain *domain, struct device *dev, bool mode) > +{ > + struct gdsc *sc = domain_to_gdsc(domain); > + > + if (sc->rsupply && !regulator_is_enabled(sc->rsupply)) { > + pr_err("Cannot set mode while parent is disabled\n"); > + return -EIO; > + } > + > + return gdsc_hwctrl(sc, mode); > +} > + > +static bool gdsc_get_hwmode(struct generic_pm_domain *domain, struct device *dev) > +{ > + struct gdsc *sc = domain_to_gdsc(domain); > + u32 val; > + int ret; > + > + ret = regmap_read(sc->regmap, sc->gdscr, &val); > + if (ret) > + return ret; > + > + if (val & HW_CONTROL_MASK) > + return true; > + > + return false; > +} > + > static int gdsc_init(struct gdsc *sc) > { > u32 mask, val; > @@ -451,6 +479,10 @@ static int gdsc_init(struct gdsc *sc) > sc->pd.power_off = gdsc_disable; > if (!sc->pd.power_on) > sc->pd.power_on = gdsc_enable; > + if (sc->flags & HW_CTRL_TRIGGER) { > + sc->pd.set_hwmode_dev = gdsc_set_hwmode; > + sc->pd.get_hwmode_dev = gdsc_get_hwmode; > + } > > ret = pm_genpd_init(&sc->pd, NULL, !on); > if (ret) > diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h > index 803512688336..1e2779b823d1 100644 > --- a/drivers/clk/qcom/gdsc.h > +++ b/drivers/clk/qcom/gdsc.h > @@ -67,6 +67,7 @@ struct gdsc { > #define ALWAYS_ON BIT(6) > #define RETAIN_FF_ENABLE BIT(7) > #define NO_RET_PERIPH BIT(8) > +#define HW_CTRL_TRIGGER BIT(9) > struct reset_controller_dev *rcdev; > unsigned int *resets; > unsigned int reset_count; > > -- > 2.34.1 > -- With best wishes Dmitry