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Message-ID: <73a332db-14d3-a5b6-331a-d52ffb27ee63@quicinc.com>
Date:   Thu, 2 Nov 2023 15:46:45 +0530
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Subject: Re: [PATCH v1 1/3] PCI: qcom: Enable cache coherency for SA8775P RC
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To:     Konrad Dybcio <konrad.dybcio@linaro.org>, <agross@kernel.org>,
        <andersson@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <conor+dt@kernel.org>, <mani@kernel.org>, <robh+dt@kernel.org>
CC:     <quic_shazhuss@quicinc.com>, <quic_nitegupt@quicinc.com>,
        <quic_ramkri@quicinc.com>, <quic_nayiluri@quicinc.com>,
        <dmitry.baryshkov@linaro.org>, <robh@kernel.org>,
        <quic_krichai@quicinc.com>, <quic_vbadigan@quicinc.com>,
        <quic_parass@quicinc.com>, <quic_schintav@quicinc.com>,
        <quic_shijjose@quicinc.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
References: <1698767186-5046-1-git-send-email-quic_msarkar@quicinc.com>
 <1698767186-5046-2-git-send-email-quic_msarkar@quicinc.com>
 <e5ee7051-d867-453f-98a7-3a8aea402607@linaro.org>
From:   Mrinmay Sarkar <quic_msarkar@quicinc.com>
In-Reply-To: <e5ee7051-d867-453f-98a7-3a8aea402607@linaro.org>
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On 10/31/2023 10:20 PM, Konrad Dybcio wrote:
> On 31.10.2023 16:46, Mrinmay Sarkar wrote:
>> This change will enable cache snooping logic to support
>> cache coherency for SA8755P RC platform.
> 8775
>
>> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 6902e97..6f240fc 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -51,6 +51,7 @@
>>   #define PARF_SID_OFFSET				0x234
>>   #define PARF_BDF_TRANSLATE_CFG			0x24c
>>   #define PARF_SLV_ADDR_SPACE_SIZE		0x358
>> +#define PCIE_PARF_NO_SNOOP_OVERIDE		0x3d4
>>   #define PARF_DEVICE_TYPE			0x1000
>>   #define PARF_BDF_TO_SID_TABLE_N			0x2000
>>   
>> @@ -117,6 +118,9 @@
>>   /* PARF_LTSSM register fields */
>>   #define LTSSM_EN				BIT(8)
>>   
>> +/* PARF_NO_SNOOP_OVERIDE register value */
> override
>> +#define NO_SNOOP_OVERIDE_EN			0xa
> is this actually some magic value and not BIT(1) | BIT(3)?
we need to set 1st and 3rd bit. yes, we can use BIT(1) | BIT(3).
>
>>   /* PARF_DEVICE_TYPE register fields */
>>   #define DEVICE_TYPE_RC				0x4
>>   
>> @@ -961,6 +965,13 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>>   
>>   static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
>>   {
>> +	struct dw_pcie *pci = pcie->pci;
>> +	struct device *dev = pci->dev;
>> +
>> +	/* Enable cache snooping for SA8775P */
>> +	if (of_device_is_compatible(dev->of_node, "qcom,pcie-sa8775p"))
>> +		writel(NO_SNOOP_OVERIDE_EN, pcie->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
> Why only for 8775 and not for other v2.7, or perhaps all other
> revisions?
yes this is only required for 8775 due to hw requirement we need to enable
cache snooping from the register level for 8775.
> Konrad
Thanks,
Mrinmay