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Message-ID: <9bc9514044063bc57155fb786f970ca1d69758b4.camel@redhat.com>
Subject: Re: [PATCH net 6/7] net: hns3: fix VF reset fail issue
From:   Paolo Abeni <pabeni@redhat.com>
To:     Jijie Shao <shaojijie@huawei.com>, yisen.zhuang@huawei.com,
        salil.mehta@huawei.com, davem@davemloft.net, edumazet@google.com,
        kuba@kernel.org
Cc:     shenjian15@huawei.com, wangjie125@huawei.com,
        liuyonglong@huawei.com, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
Date:   Thu, 02 Nov 2023 11:45:48 +0100
In-Reply-To: <20231028025917.314305-7-shaojijie@huawei.com>
References: <20231028025917.314305-1-shaojijie@huawei.com>
         <20231028025917.314305-7-shaojijie@huawei.com>
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On Sat, 2023-10-28 at 10:59 +0800, Jijie Shao wrote:
> Currently the reset process in hns3 and firmware watchdog init process is
> asynchronous. We think firmware watchdog initialization is completed
> before VF clear the interrupt source. However, firmware initialization
> may not complete early. So VF will receive multiple reset interrupts
> and fail to reset.
>=20
> So we add delay before VF interrupt source and 5 ms delay
> is enough to avoid second reset interrupt.
>=20
> Fixes: 427900d27d86 ("net: hns3: fix the timing issue of VF clearing inte=
rrupt sources")
> Signed-off-by: Jijie Shao <shaojijie@huawei.com>
> ---
>  .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c   | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>=20
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/=
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
> index 1c62e58ff6d8..7b87da031be6 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
> @@ -1924,8 +1924,14 @@ static void hclgevf_service_task(struct work_struc=
t *work)
>  	hclgevf_mailbox_service_task(hdev);
>  }
> =20
> -static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regc=
lr)
> +static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regc=
lr,
> +				      bool need_dalay)
>  {
> +#define HCLGEVF_RESET_DELAY		5
> +
> +	if (need_dalay)
> +		mdelay(HCLGEVF_RESET_DELAY);

5ms delay in an interrupt handler is quite a lot. What about scheduling
a timer from the IH to clear the register when such delay is needed?

Thanks!

Paolo