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From:   Radoslaw Biernacki <biernacki@google.com>
Date:   Thu, 2 Nov 2023 15:18:33 +0100
Message-ID: <CAM4=RnLqQPkMNPqFPeVnzrogcWNe3j-=hBWkFHgGovd97Y_FUg@mail.gmail.com>
Subject: Re: [PATCH 1/2] mmc: cqhci: Add a quirk to clear stale TC
To:     =?UTF-8?Q?Kornel_Dul=C4=99ba?= <korneld@chromium.org>
Cc:     Adrian Hunter <adrian.hunter@intel.com>, linux-mmc@vger.kernel.org,
        linux-kernel@vger.kernel.org, Ulf Hansson <ulf.hansson@linaro.org>,
        Gwendal Grignou <gwendal@chromium.org>
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On Thu, Nov 2, 2023 at 3:07=E2=80=AFPM Kornel Dul=C4=99ba <korneld@chromium=
.org> wrote:
>
> On Thu, Nov 02, 2023 at 01:01:22PM +0200, Adrian Hunter wrote:
> > On 2/11/23 11:21, Kornel Dul=C4=99ba wrote:
> > > On Mon, Oct 30, 2023 at 8:31=E2=80=AFPM Adrian Hunter <adrian.hunter@=
intel.com> wrote:
> > >>
> > >> On 27/10/23 17:56, Kornel Dul=C4=99ba wrote:
> > >>> This fix addresses a stale task completion event issued right after=
 the
> > >>> CQE recovery. As it's a hardware issue the fix is done in form of a
> > >>> quirk.
> > >>>
> > >>> When error interrupt is received the driver runs recovery logic is =
run.
> > >>> It halts the controller, clears all pending tasks, and then re-enab=
les
> > >>> it. On some platforms a stale task completion event is observed,
> > >>> regardless of the CQHCI_CLEAR_ALL_TASKS bit being set.
> > >>>
> > >>> This results in either:
> > >>> a) Spurious TC completion event for an empty slot.
> > >>> b) Corrupted data being passed up the stack, as a result of prematu=
re
> > >>>    completion for a newly added task.
> > >>>
> > >>> To fix that re-enable the controller, clear task completion bits,
> > >>> interrupt status register and halt it again.
> > >>> This is done at the end of the recovery process, right before inter=
rupts
> > >>> are re-enabled.
> > >>>
> > >>> Signed-off-by: Kornel Dul=C4=99ba <korneld@chromium.org>
> > >>> ---
> > >>>  drivers/mmc/host/cqhci-core.c | 42 +++++++++++++++++++++++++++++++=
++++
> > >>>  drivers/mmc/host/cqhci.h      |  1 +
> > >>>  2 files changed, 43 insertions(+)
> > >>>
> > >>> diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci=
-core.c
> > >>> index b3d7d6d8d654..e534222df90c 100644
> > >>> --- a/drivers/mmc/host/cqhci-core.c
> > >>> +++ b/drivers/mmc/host/cqhci-core.c
> > >>> @@ -1062,6 +1062,45 @@ static void cqhci_recover_mrqs(struct cqhci_=
host *cq_host)
> > >>>  /* CQHCI could be expected to clear it's internal state pretty qui=
ckly */
> > >>>  #define CQHCI_CLEAR_TIMEOUT          20
> > >>>
> > >>> +/*
> > >>> + * During CQE recovery all pending tasks are cleared from the
> > >>> + * controller and its state is being reset.
> > >>> + * On some platforms the controller sets a task completion bit for
> > >>> + * a stale(previously cleared) task right after being re-enabled.
> > >>> + * This results in a spurious interrupt at best and corrupted data
> > >>> + * being passed up the stack at worst. The latter happens when
> > >>> + * the driver enqueues a new request on the problematic task slot
> > >>> + * before the "spurious" task completion interrupt is handled.
> > >>> + * To fix it:
> > >>> + * 1. Re-enable controller by clearing the halt flag.
> > >>> + * 2. Clear interrupt status and the task completion register.
> > >>> + * 3. Halt the controller again to be consistent with quirkless lo=
gic.
> > >>> + *
> > >>> + * This assumes that there are no pending requests on the queue.
> > >>> + */
> > >>> +static void cqhci_quirk_clear_stale_tc(struct cqhci_host *cq_host)
> > >>> +{
> > >>> +     u32 reg;
> > >>> +
> > >>> +     WARN_ON(cq_host->qcnt);
> > >>> +     cqhci_writel(cq_host, 0, CQHCI_CTL);
> > >>> +     if ((cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)) {
> > >>> +             pr_err("%s: cqhci: CQE failed to exit halt state\n",
> > >>> +                     mmc_hostname(cq_host->mmc));
> > >>> +     }
> > >>> +     reg =3D cqhci_readl(cq_host, CQHCI_TCN);
> > >>> +     cqhci_writel(cq_host, reg, CQHCI_TCN);
> > >>> +     reg =3D cqhci_readl(cq_host, CQHCI_IS);
> > >>> +     cqhci_writel(cq_host, reg, CQHCI_IS);
> > >>> +
> > >>> +     /*
> > >>> +      * Halt the controller again.
> > >>> +      * This is only needed so that we're consistent across quirk
> > >>> +      * and quirkless logic.
> > >>> +      */
> > >>> +     cqhci_halt(cq_host->mmc, CQHCI_FINISH_HALT_TIMEOUT);
> > >>> +}
> > >>
> > >> Thanks a lot for tracking this down!
> > >>
> > >> It could be that the "un-halt" starts a task, so it would be
> > >> better to force the "clear" to work if possible, which
> > >> should be the case if CQE is disabled.
> > >>
> > >> Would you mind trying the code below?  Note the increased
> > >> CQHCI_START_HALT_TIMEOUT helps avoid trying to clear tasks
> > >> when CQE has not halted.
> > >
> > > I've run a quick test and it works just fine.
> >
> > Thank you!
> >
> > > Your approach looks better than what I proposed, since as you
> > > mentioned, doing it like this avoids some weird side effects, e.g. DM=
A
> > > to freed memory.
> > > Do you plan to include it in the other series that you posted yesterd=
ay?
> >
> > Yes I will do that
>
> Feel free to add "Tested-by: Kornel Dul=C4=99ba <korneld@chromium.org>" a=
nd
> maybe "Reported-by".

I do not want to be you advocate Kornel, but I think you earned a
Co-developed-by
That was a lot of work.