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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698947170; x=1699551970; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G85pRGyLip1+tcQHyAvlsC1xDG3Jc9lQ+KHYjFzzSQc=; b=vMoJTspv4WThE+uHlxgGUkKumnlD8ja5oBw+K6RCDMUv8o16prV6PmUkg/PCySFquk yppQNZ8ZSNOHG+dTQ/Kscsacb/FFvEcJ9MSqdL2gXgF4LC52TrFp9OD6asYNnHXuqWZU x9emHFAfbvsjiyqFfuH7VmzVX7iOEMCa2tbE5PIo+GAkZfi/YXm76O1Y7NbRpUUNYw09 jwm4wET9crFAO3lV0UlHJSn1Dux/eZgUuhWjdAsnFGdvDMNg6xoriGS5xkc9Qnx1n0N6 YKuZ2dvE+5r6O51VOaSFMZJJsrs15eULizub28CSmGBQbnyCrVpOrSag3x1qeWH6K9Er HT5A== X-Gm-Message-State: AOJu0YzKdIaqKsqlTIiYwMj5vXoMK55Snp9outDhW53rqVUzov//2xrN zDbME3ln1n8OvsKflSYL4YzFgppAhgKstiQ5O1F5cmFKiJBp600qY6XreQ== X-Received: by 2002:a50:f60b:0:b0:543:3f97:aa0f with SMTP id c11-20020a50f60b000000b005433f97aa0fmr106457edn.4.1698947169816; Thu, 02 Nov 2023 10:46:09 -0700 (PDT) MIME-Version: 1.0 References: <20231031090613.2872700-1-dapeng1.mi@linux.intel.com> <20231031090613.2872700-2-dapeng1.mi@linux.intel.com> <85706bd7-7df0-4d4b-932c-d807ddb14f9e@linux.intel.com> In-Reply-To: <85706bd7-7df0-4d4b-932c-d807ddb14f9e@linux.intel.com> From: Jim Mattson Date: Thu, 2 Nov 2023 10:45:55 -0700 Message-ID: Subject: Re: [Patch 1/2] KVM: x86/pmu: Add Intel CPUID-hinted TopDown slots event To: "Mi, Dapeng" Cc: "Liang, Kan" , Sean Christopherson , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Dapeng Mi , Like Xu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.4 required=5.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 02 Nov 2023 10:46:25 -0700 (PDT) On Wed, Nov 1, 2023 at 7:07=E2=80=AFPM Mi, Dapeng wrote: > > > On 11/1/2023 9:33 PM, Liang, Kan wrote: > > > > On 2023-10-31 11:31 p.m., Mi, Dapeng wrote: > >> On 11/1/2023 11:04 AM, Jim Mattson wrote: > >>> On Tue, Oct 31, 2023 at 6:59=E2=80=AFPM Mi, Dapeng > >>> wrote: > >>>> On 11/1/2023 2:22 AM, Jim Mattson wrote: > >>>>> On Tue, Oct 31, 2023 at 1:58=E2=80=AFAM Dapeng Mi > >>>>> wrote: > >>>>>> This patch adds support for the architectural topdown slots event > >>>>>> which > >>>>>> is hinted by CPUID.0AH.EBX. > >>>>> Can't a guest already program an event selector to count event sele= ct > >>>>> 0xa4, unit mask 1, unless the event is prohibited by > >>>>> KVM_SET_PMU_EVENT_FILTER? > >>>> Actually defining this new slots arch event is to do the sanity chec= k > >>>> for supported arch-events which is enumerated by CPUID.0AH.EBX. > >>>> Currently vPMU would check if the arch event from guest is supported= by > >>>> KVM. If not, it would be rejected just like intel_hw_event_available= () > >>>> shows. > >>>> > >>>> If we don't add the slots event in the intel_arch_events[] array, gu= est > >>>> may program the slots event and pass the sanity check of KVM on a > >>>> platform which actually doesn't support slots event and program the > >>>> event on a real GP counter and got an invalid count. This is not > >>>> correct. > >>> On physical hardware, it is possible to program a GP counter with the > >>> event selector and unit mask of the slots event whether or not the > >>> platform supports it. Isn't KVM wrong to disallow something that a > >>> physical CPU allows? > >> > >> Yeah, I agree. But I'm not sure if this is a flaw on PMU driver. If an > >> event is not supported by the hardware, we can't predict the PMU's > >> behavior and a meaningless count may be returned and this could mislea= d > >> the user. > > The user can program any events on the GP counter. The perf doesn't > > limit it. For the unsupported event, 0 should be returned. Please keep > > in mind, the event list keeps updating. If the kernel checks for each > > event, it could be a disaster. I don't think it's a flaw. > > > Thanks Kan, it would be ok as long as 0 is always returned for > unsupported events. IMO, it's a nice to have feature that KVM does this > sanity check for supported arch events, it won't break anything. The hardware PMU most assuredly does not return 0 for unsupported events. For example, if I use host perf to sample event selector 0xa4 unit mask 1 on a Broadwell host (406f1), I get... # perf stat -e r01a4 sleep 10 Performance counter stats for 'sleep 10': 386,964 r01a4 10.000907211 seconds time elapsed Broadwell does not advertise support for architectural event 7 in CPUID.0AH:EBX, so KVM will refuse to measure this event inside a guest. That seems broken to me. > > > > > Thanks, > > Kan > >> Add Kan to confirm this. > >> > >> Hi Kan, > >> > >> Have you any comments on this? Thanks. > >> > >> > >>>>> AFAICT, this change just enables event filtering based on > >>>>> CPUID.0AH:EBX[bit 7] (though it's not clear to me why two independe= nt > >>>>> mechanisms are necessary for event filtering). > >>>> IMO, these are two different things. this change is just to enable t= he > >>>> supported arch events check for slot events, the event filtering is > >>>> another thing. > >>> How is clearing CPUID.0AH:EBX[bit 7] any different from putting {even= t > >>> select 0xa4, unit mask 1} in a deny list with the PMU event filter? > >> I think there is no difference in the conclusion but with two differen= t > >> methods. > >> > >>