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Date:   Thu, 2 Nov 2023 13:19:55 -0700
From:   Alison Schofield <alison.schofield@intel.com>
To:     Terry Bowman <terry.bowman@amd.com>
Cc:     vishal.l.verma@intel.com, ira.weiny@intel.com, bwidawsk@kernel.org,
        dan.j.williams@intel.com, dave.jiang@intel.com,
        Jonathan.Cameron@huawei.com, linux-cxl@vger.kernel.org,
        Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] cxl/pci: Change CXL AER support check to use native AER
Message-ID: <ZUQEa1q/R2KBF/3W@aschofie-mobl2>
References: <20231102155232.1421261-1-terry.bowman@amd.com>
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On Thu, Nov 02, 2023 at 10:52:32AM -0500, Terry Bowman wrote:
> Native CXL protocol errors are delivered to the OS through AER
> reporting. The owner of AER owns CXL Protocol error management with
> respect to _OSC negotiation.[1] CXL device errors are handled by a
> separate interrupt with native control gated by _OSC control field
> 'CXL Memory Error Reporting Control'.
> 
> The CXL driver incorrectly checks for 'CXL Memory Error Reporting
> Control' before accessing AER registers and caching RCH downport
> AER registers. Replace the current check in these 2 cases with
> native AER checks.

Hi Terry,  Does this have a user visible impact? 

Alison

>
--snip