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Received: from DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) by BY5PR12MB4099.namprd12.prod.outlook.com (2603:10b6:a03:20f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.21; Thu, 2 Nov 2023 23:24:36 +0000 Received: from DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::26b0:6759:d910:2dad]) by DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::26b0:6759:d910:2dad%5]) with mapi id 15.20.6954.019; Thu, 2 Nov 2023 23:24:36 +0000 Message-ID: <81376530-ecc7-4457-bfed-2e8b65f69f4e@amd.com> Date: Thu, 2 Nov 2023 18:24:33 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] cxl/pci: Change CXL AER support check to use native AER Content-Language: en-US To: Dan Williams , Alison Schofield Cc: vishal.l.verma@intel.com, ira.weiny@intel.com, bwidawsk@kernel.org, dave.jiang@intel.com, Jonathan.Cameron@huawei.com, linux-cxl@vger.kernel.org, Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com, linux-kernel@vger.kernel.org References: <20231102155232.1421261-1-terry.bowman@amd.com> <65441103b3b1b_44d229485@dwillia2-xfh.jf.intel.com.notmuch> <65441514c8494_244c8f294af@dwillia2-xfh.jf.intel.com.notmuch> From: Terry Bowman In-Reply-To: <65441514c8494_244c8f294af@dwillia2-xfh.jf.intel.com.notmuch> Content-Type: text/plain; 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Thu, 02 Nov 2023 16:30:27 -0700 (PDT) Hi Dan and Allison, On 11/2/23 16:31, Dan Williams wrote: > Dan Williams wrote: >> Alison Schofield wrote: >>> On Thu, Nov 02, 2023 at 10:52:32AM -0500, Terry Bowman wrote: >>>> Native CXL protocol errors are delivered to the OS through AER >>>> reporting. The owner of AER owns CXL Protocol error management with >>>> respect to _OSC negotiation.[1] CXL device errors are handled by a >>>> separate interrupt with native control gated by _OSC control field >>>> 'CXL Memory Error Reporting Control'. >>>> >>>> The CXL driver incorrectly checks for 'CXL Memory Error Reporting >>>> Control' before accessing AER registers and caching RCH downport >>>> AER registers. Replace the current check in these 2 cases with >>>> native AER checks. >>> >>> Hi Terry, Does this have a user visible impact? >> >> Saw this after I applied it. It is good feedback in general. >> >> The reason I did not ask for this clarification was that this is fixing >> brand new code and was just using the wrong flag, so I had the context. >> A backporter will never need to make a judgement call about this patch. >> >> The end user impact is that CXL protocol errors that could be handled by >> AER will not be handled if Linux failed to negotiate memory error >> handling. Memory errors are strictly related to memory-error-record >> events, not protocol errors. > Right, end user impact is RCH error handling will require using native memory error/event _OSC control inorder for protocol errors to be logged. > However, to that point the "Fixes:" tag looks wrong, it should be: > > f05fd10d138d cxl/pci: Add RCH downstream port AER register discovery Correct, it is f05fd10d138d. Regards, Terry