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From:   Atul Dhudase <quic_adhudase@quicinc.com>
To:     agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
        swboyd@chromium.org, isaacm@codeaurora.org, dianders@chromium.org
Cc:     linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        Atul Dhudase <quic_adhudase@quicinc.com>
Subject: [PATCH] soc: qcom: llcc: Fix dis_cap_alloc and retain_on_pc configuration
Date:   Fri,  3 Nov 2023 16:27:12 +0530
Message-Id: <20231103105712.1159213-1-quic_adhudase@quicinc.com>
MIME-Version: 1.0
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Precedence: bulk

While programming dis_cap_alloc and retain_on_pc, set a bit
corresponding to a specific SCID without disturbing the
previously configured bits.

Fixes: c14e64b46944 ("soc: qcom: llcc: Support chipsets that can write to llcc")
Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 674abd0d6700..509d972c1bd9 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -941,15 +941,15 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
 		u32 disable_cap_alloc, retain_pc;

 		disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
-		ret = regmap_write(drv_data->bcast_regmap,
-				LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
+		ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC,
+				BIT(config->slice_id), disable_cap_alloc);
 		if (ret)
 			return ret;

 		if (drv_data->version < LLCC_VERSION_4_1_0_0) {
 			retain_pc = config->retain_on_pc << config->slice_id;
-			ret = regmap_write(drv_data->bcast_regmap,
-					LLCC_TRP_PCB_ACT, retain_pc);
+			ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_PCB_ACT,
+					BIT(config->slice_id), retain_pc);
 			if (ret)
 				return ret;
 		}
--
2.25.1