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Date:   Fri, 3 Nov 2023 09:29:12 -0400
From:   Ben Wolsieffer <ben.wolsieffer@hefring.com>
To:     Conor Dooley <conor@kernel.org>
Cc:     linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Mark Brown <broonie@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Alain Volmat <alain.volmat@foss.st.com>,
        Erwan Leray <erwan.leray@foss.st.com>,
        Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Subject: Re: [PATCH v2 3/5] dt-bindings: spi: add stm32f7-spi compatible
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Hi Conor,

On Fri, Nov 03, 2023 at 12:50:53PM +0000, Conor Dooley wrote:
> On Thu, Nov 02, 2023 at 03:37:20PM -0400, Ben Wolsieffer wrote:
> A wider range of supported word sizes and some additional buffers,
> implies that the F4 could be used as a fallback compatible. Does the
> register map change incompatibly in the process of widening the FIFOs or
> something like that?

Yes, the F4 has a single bit to select 8 or 16 bit word size, while the
F7 uses four bits to select an arbitrary word size from 4 to 16 bits.
This series supports the packing mode, to allow sending two <=8 bit
words with a single write to the FIFO, but even if we didn't want to
support this feature, the F7 would require setting the FRXTH bit (not
present in the F4) when using <=8 bit word sizes.

> 
> Cheers,
> Conor.