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References: <20231103105712.1159213-1-quic_adhudase@quicinc.com>
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From:   Doug Anderson <dianders@chromium.org>
Date:   Fri, 3 Nov 2023 07:48:21 -0700
Message-ID: <CAD=FV=Un2GnOC64AXgKa31FNZ+FM2dMbHVT8UuZXNbMUDBD=8w@mail.gmail.com>
Subject: Re: [PATCH] soc: qcom: llcc: Fix dis_cap_alloc and retain_on_pc configuration
To:     Atul Dhudase <quic_adhudase@quicinc.com>
Cc:     agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
        swboyd@chromium.org, isaacm@codeaurora.org,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
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Hi,

On Fri, Nov 3, 2023 at 3:57=E2=80=AFAM Atul Dhudase <quic_adhudase@quicinc.=
com> wrote:
>
> While programming dis_cap_alloc and retain_on_pc, set a bit
> corresponding to a specific SCID without disturbing the
> previously configured bits.
>
> Fixes: c14e64b46944 ("soc: qcom: llcc: Support chipsets that can write to=
 llcc")
> Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com>
> ---
>  drivers/soc/qcom/llcc-qcom.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 674abd0d6700..509d972c1bd9 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -941,15 +941,15 @@ static int _qcom_llcc_cfg_program(const struct llcc=
_slice_config *config,
>                 u32 disable_cap_alloc, retain_pc;
>
>                 disable_cap_alloc =3D config->dis_cap_alloc << config->sl=
ice_id;
> -               ret =3D regmap_write(drv_data->bcast_regmap,
> -                               LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_=
alloc);
> +               ret =3D regmap_update_bits(drv_data->bcast_regmap, LLCC_T=
RP_SCID_DIS_CAP_ALLOC,
> +                               BIT(config->slice_id), disable_cap_alloc)=
;
>                 if (ret)
>                         return ret;
>
>                 if (drv_data->version < LLCC_VERSION_4_1_0_0) {
>                         retain_pc =3D config->retain_on_pc << config->sli=
ce_id;
> -                       ret =3D regmap_write(drv_data->bcast_regmap,
> -                                       LLCC_TRP_PCB_ACT, retain_pc);
> +                       ret =3D regmap_update_bits(drv_data->bcast_regmap=
, LLCC_TRP_PCB_ACT,
> +                                       BIT(config->slice_id), retain_pc)=
;

Wow, that seems pretty serious. As far as I can tell this looks correct.

Reviewed-by: Douglas Anderson <dianders@chromium.org>