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Fri, 3 Nov 2023 15:21:28 +0000 Received: from TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::d870:7910:448d:fb6d]) by TYZPR01MB5556.apcprd01.prod.exchangelabs.com ([fe80::d870:7910:448d:fb6d%6]) with mapi id 15.20.6954.024; Fri, 3 Nov 2023 15:21:28 +0000 Message-ID: Date: Fri, 3 Nov 2023 23:21:20 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v2] mmc: meson-mx-sdhc: Fix initialization frozen issue To: Anand Moon Cc: ulf.hansson@linaro.org, neil.armstrong@linaro.org, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, yinxin_1989@aliyun.com, regressions@leemhuis.info, briannorris@chromium.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: From: Ziyang Huang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TMN: [R2jALOy0GfheUgjSJoqoh2FRTbcgE6yZ] X-ClientProxiedBy: TYCP286CA0064.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:31a::11) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|SI2PR01MB4300:EE_ X-MS-Office365-Filtering-Correlation-Id: 04df2f89-6ea7-4516-556d-08dbdc808cc1 X-Microsoft-Antispam: BCL:0; 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Fri, 03 Nov 2023 08:21:52 -0700 (PDT) 在 2023/10/29 21:08, Anand Moon 写道: > Hi Ziyang, > > On Tue, 10 Oct 2023 at 22:15, Ziyang Huang wrote: >> >> Commit 4bc31edebde5 ("mmc: core: Set HS clock speed before sending >> HS CMD13") set HS clock (52MHz) before switching to HS mode. For this >> freq, FCLK_DIV5 will be selected and div value is 10 (reg value is 9). >> Then we set rx_clk_phase to 11 or 15 which is out of range and make >> hardware frozen. After we send command request, no irq will be >> interrupted and the mmc driver will keep to wait for request finished, >> even durning rebooting. >> >> So let's set it to Phase 90 which should work in most cases. Then let >> meson_mx_sdhc_execute_tuning() to find the accurate value for data >> transfer. >> >> If this doesn't work, maybe need to define a factor in dts. >> >> Fixes: e4bf1b0970ef ("mmc: host: meson-mx-sdhc: new driver for the Amlogic Meson SDHC host") >> Signed-off-by: Ziyang Huang >> --- >> Changes since v1: >> Use Phase 90 instand of value 1 >> > > I have tested this patch on my Odroid C1+ board. > Please add my > > Tested-by: Anand Moon > > [alarm@alarm ~]$ sudo cat /sys/kernel/debug/mmc1/ios > clock: 100000000 Hz > actual clock: 94444445 Hz > vdd: 21 (3.3 ~ 3.4 V) > bus mode: 2 (push-pull) > chip select: 0 (don't care) > power mode: 2 (on) > bus width: 3 (8 bits) > timing spec: 9 (mmc HS200) > signal voltage: 1 (1.80 V) > driver type: 0 (driver type B) > [alarm@alarm ~]$ sync && dd if=/dev/zero of=~/testfile bs=100M count=1 > oflag=dsync && sync > 1+0 records in > 1+0 records out > 104857600 bytes (105 MB, 100 MiB) copied, 5.70235 s, 18.4 MB/s > [alarm@alarm ~]$ sync && dd if=~/testfile of=/dev/null bs=100M count=1 > iflag=dsync && sync > 1+0 records in > 1+0 records out > 104857600 bytes (105 MB, 100 MiB) copied, 0.20267 s, 517 MB/s > > Thanks > -Anand > Oh, thank you.