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Date:   Sat, 04 Nov 2023 09:56:40 +0000
Message-ID: <87o7g96duv.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Fang Xiang <fangxiang3@xiaomi.com>
Cc:     <tglx@linutronix.de>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v4] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.
In-Reply-To: <20231030083256.4345-1-fangxiang3@xiaomi.com>
References: <20231030083256.4345-1-fangxiang3@xiaomi.com>
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On Mon, 30 Oct 2023 08:32:56 +0000,
Fang Xiang <fangxiang3@xiaomi.com> wrote:
> 
> In non-coherent GIC design, ITS tables should be clean and flushed
> to the PoV of the ITS before writing GITS_BASER<n> registers, otherwise
> the ITS would read dirty tables and lead to UNPREDICTABLE behaviors.
> 
> The ITS always got clean tables in initialization with this fix, by
> observing the signals from GIC.
> 
> Furthermore, hoist the quirked non-shareable attributes earlier to
> save effort in tables setup.
> 
> Suggested-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
> Tested-by: Fang Xiang <fangxiang3@xiaomi.com>

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.