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From:   Thomas Gleixner <tglx@linutronix.de>
To:     Marc Zyngier <maz@kernel.org>, Fang Xiang <fangxiang3@xiaomi.com>
Cc:     linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4] irqchip/gic-v3-its: Flush ITS tables before writing
 GITS_BASER<n> registers in non-coherent GIC designs.
In-Reply-To: <87o7g96duv.wl-maz@kernel.org>
References: <20231030083256.4345-1-fangxiang3@xiaomi.com>
 <87o7g96duv.wl-maz@kernel.org>
Date:   Sun, 05 Nov 2023 09:55:11 +0100
Message-ID: <87bkc8inps.ffs@tglx>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk

On Sat, Nov 04 2023 at 09:56, Marc Zyngier wrote:
> On Mon, 30 Oct 2023 08:32:56 +0000,
> Fang Xiang <fangxiang3@xiaomi.com> wrote:
>> 
>> In non-coherent GIC design, ITS tables should be clean and flushed
>> to the PoV of the ITS before writing GITS_BASER<n> registers, otherwise
>> the ITS would read dirty tables and lead to UNPREDICTABLE behaviors.
>> 
>> The ITS always got clean tables in initialization with this fix, by
>> observing the signals from GIC.
>> 
>> Furthermore, hoist the quirked non-shareable attributes earlier to
>> save effort in tables setup.
>> 
>> Suggested-by: Marc Zyngier <maz@kernel.org>
>> Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
>> Tested-by: Fang Xiang <fangxiang3@xiaomi.com>
>
> Reviewed-by: Marc Zyngier <maz@kernel.org>

Shouldn't this have a Fixes tag? My guess is:

a8707f553884 ("irqchip/gic-v3: Add Rockchip 3588001 erratum workaround")