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Mon, 06 Nov 2023 06:28:29 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A66SSH4008883 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 6 Nov 2023 06:28:28 GMT Received: from [10.214.227.50] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Sun, 5 Nov 2023 22:28:23 -0800 Message-ID: <482bf12a-03d1-4054-a2df-3bf82d359e4c@quicinc.com> Date: Mon, 6 Nov 2023 11:58:23 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] iommu/arm-smmu: re-enable context caching in smmu reset operation Content-Language: en-US To: Konrad Dybcio , , , , , , , , CC: , , , References: <20231103215124.1095-1-quic_bibekkum@quicinc.com> <20231103215124.1095-4-quic_bibekkum@quicinc.com> <26af3ecc-8b3f-4b10-b594-eae57de501cb@linaro.org> From: Bibek Kumar Patro In-Reply-To: <26af3ecc-8b3f-4b10-b594-eae57de501cb@linaro.org> Content-Type: text/plain; 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Sun, 05 Nov 2023 22:28:53 -0800 (PST) On 11/4/2023 5:00 PM, Konrad Dybcio wrote: > > > On 11/3/23 22:51, Bibek Kumar Patro wrote: >> Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs >> through SoC specific reset ops, which is disabled in the default MMU-500 >> reset ops, but is expected for context banks using ACTLR register to >> retain the prefetch value during reset and runtime suspend. >> >> Signed-off-by: Bibek Kumar Patro >> --- >>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++---- >>   1 file changed, 22 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> index 590b7c285299..f342b4778cf1 100644 >> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> @@ -457,11 +457,29 @@ static int qcom_smmu_def_domain_type(struct >> device *dev) >>       return match ? IOMMU_DOMAIN_IDENTITY : 0; >>   } >> >> +#define ARM_MMU500_ACTLR_CPRE          BIT(1) >> + >> +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) >> +{ >> +    int i; >> +    u32 reg; >> + >> +    arm_mmu500_reset(smmu); >> + >> +        for (i = 0; i < smmu->num_context_banks; ++i) { > This loop deserves a comment above it like > > /* Re-enable context caching after reset */ > Ack, thanks for this suggestion, this might help to explain this addition. I would incorporate this in next patch. regards, Bibek > Konrad