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From:   Victor Shih <victorshihgli@gmail.com>
Date:   Mon, 6 Nov 2023 16:55:53 +0800
Message-ID: <CAK00qKDvdDBJ9zrBh=9anCArOZUis8-kE5bRx=owjD_pe4ZDCg@mail.gmail.com>
Subject: Re: [PATCH V2] mmc: sdhci-pci-gli: GL975[05]: Mask the replay timer
 timeout of AER
To:     Ulf Hansson <ulf.hansson@linaro.org>
Cc:     adrian.hunter@intel.com, linux-mmc@vger.kernel.org,
        linux-kernel@vger.kernel.org, benchuanggli@gmail.com,
        HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw,
        SeanHY.Chen@genesyslogic.com.tw, kai.heng.feng@canonical.com,
        Victor Shih <victor.shih@genesyslogic.com.tw>
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On Fri, Nov 3, 2023 at 6:28=E2=80=AFPM Ulf Hansson <ulf.hansson@linaro.org>=
 wrote:
>
> On Fri, 3 Nov 2023 at 11:13, Victor Shih <victorshihgli@gmail.com> wrote:
> >
> > Hi, Ulf
> >
> > Please help review this patch and give me some advice.
> > I look forward to your reply.
> >
> > Thanks, Victor Shih
>
> I don't have in-depth knowledge of how to properly solve this for pci,
> so I am relying on Kai and others to help review.
>

Hi, Ulf

This is a standalone patch, this patch only solves the warning
messages that will
 often appear in the system log when the system accesses the GL975x PCI con=
fig.

As I discussed with Kai-Heng at the end of
[V1] mmc: sdhci-pci-gli: GL975[05]: Mask the replay timer timeout of AER,
Kai-Heng will be submitting a patch for the PCIe layer to solve the
situation he encountered.
I will also help Kai-Heng test when he submits the patch.

Thanks, Victor Shih

> >
> > On Wed, Oct 18, 2023 at 6:33=E2=80=AFPM Victor Shih <victorshihgli@gmai=
l.com> wrote:
> > >
> > > From: Victor Shih <victor.shih@genesyslogic.com.tw>
> > >
> > > Due to a flaw in the hardware design, the GL975x replay timer frequen=
tly
> > > times out when ASPM is enabled. As a result, the warning messages tha=
t will
> > > often appear in the system log when the system accesses the GL975x
> > > PCI config. Therefore, the replay timer timeout must be masked.
> > >
> > > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
>
> The code looks good to me, but let's allow Kai to get some time to
> come back to this before I apply it.
>
> Kind regards
> Uffe
>
> > > ---
> > >
> > > Updates in V2:
> > >  - Modify the commit message.
> > >
> > > ---
> > >
> > >  drivers/mmc/host/sdhci-pci-gli.c | 16 ++++++++++++++++
> > >  1 file changed, 16 insertions(+)
> > >
> > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhc=
i-pci-gli.c
> > > index d83261e857a5..d8a991b349a8 100644
> > > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > > @@ -28,6 +28,9 @@
> > >  #define PCI_GLI_9750_PM_CTRL   0xFC
> > >  #define   PCI_GLI_9750_PM_STATE          GENMASK(1, 0)
> > >
> > > +#define PCI_GLI_9750_CORRERR_MASK                              0x214
> > > +#define   PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT         BIT=
(12)
> > > +
> > >  #define SDHCI_GLI_9750_CFG2          0x848
> > >  #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
> > >  #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
> > > @@ -152,6 +155,9 @@
> > >  #define PCI_GLI_9755_PM_CTRL     0xFC
> > >  #define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> > >
> > > +#define PCI_GLI_9755_CORRERR_MASK                              0x214
> > > +#define   PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT         BIT=
(12)
> > > +
> > >  #define SDHCI_GLI_9767_GM_BURST_SIZE                   0x510
> > >  #define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET    BIT(8)
> > >
> > > @@ -561,6 +567,11 @@ static void gl9750_hw_setting(struct sdhci_host =
*host)
> > >         value &=3D ~PCI_GLI_9750_PM_STATE;
> > >         pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
> > >
> > > +       /* mask the replay timer timeout of AER */
> > > +       pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value=
);
> > > +       value |=3D PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
> > > +       pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value=
);
> > > +
> > >         gl9750_wt_off(host);
> > >  }
> > >
> > > @@ -770,6 +781,11 @@ static void gl9755_hw_setting(struct sdhci_pci_s=
lot *slot)
> > >         value &=3D ~PCI_GLI_9755_PM_STATE;
> > >         pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> > >
> > > +       /* mask the replay timer timeout of AER */
> > > +       pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value=
);
> > > +       value |=3D PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
> > > +       pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value=
);
> > > +
> > >         gl9755_wt_off(pdev);
> > >  }
> > >
> > > --
> > > 2.25.1
> > >