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Message-ID: <d18a2569-ebc3-484f-927a-5e3682457469@intel.com>
Date:   Mon, 6 Nov 2023 11:29:07 +0200
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Subject: Re: [PATCH V2] mmc: sdhci-pci-gli: GL975[05]: Mask the replay timer
 timeout of AER
Content-Language: en-US
To:     Victor Shih <victorshihgli@gmail.com>, ulf.hansson@linaro.org
Cc:     linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
        benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw,
        Greg.tu@genesyslogic.com.tw, SeanHY.Chen@genesyslogic.com.tw,
        kai.heng.feng@canonical.com,
        Victor Shih <victor.shih@genesyslogic.com.tw>
References: <20231018103337.34622-1-victorshihgli@gmail.com>
From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
 Business Identity Code: 0357606 - 4, Domiciled in Helsinki
In-Reply-To: <20231018103337.34622-1-victorshihgli@gmail.com>
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On 18/10/23 13:33, Victor Shih wrote:
> From: Victor Shih <victor.shih@genesyslogic.com.tw>
> 
> Due to a flaw in the hardware design, the GL975x replay timer frequently
> times out when ASPM is enabled. As a result, the warning messages that will
> often appear in the system log when the system accesses the GL975x
> PCI config. Therefore, the replay timer timeout must be masked.
> 
> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
> 
> Updates in V2:
>  - Modify the commit message.
> 
> ---
> 
>  drivers/mmc/host/sdhci-pci-gli.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index d83261e857a5..d8a991b349a8 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -28,6 +28,9 @@
>  #define PCI_GLI_9750_PM_CTRL	0xFC
>  #define   PCI_GLI_9750_PM_STATE	  GENMASK(1, 0)
>  
> +#define PCI_GLI_9750_CORRERR_MASK				0x214
> +#define   PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT	  BIT(12)
> +
>  #define SDHCI_GLI_9750_CFG2          0x848
>  #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
>  #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
> @@ -152,6 +155,9 @@
>  #define PCI_GLI_9755_PM_CTRL     0xFC
>  #define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
>  
> +#define PCI_GLI_9755_CORRERR_MASK				0x214
> +#define   PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT	  BIT(12)
> +
>  #define SDHCI_GLI_9767_GM_BURST_SIZE			0x510
>  #define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET	  BIT(8)
>  
> @@ -561,6 +567,11 @@ static void gl9750_hw_setting(struct sdhci_host *host)
>  	value &= ~PCI_GLI_9750_PM_STATE;
>  	pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
>  
> +	/* mask the replay timer timeout of AER */
> +	pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
> +	value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
> +	pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
> +
>  	gl9750_wt_off(host);
>  }
>  
> @@ -770,6 +781,11 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
>  	value &= ~PCI_GLI_9755_PM_STATE;
>  	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
>  
> +	/* mask the replay timer timeout of AER */
> +	pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);
> +	value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
> +	pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);
> +
>  	gl9755_wt_off(pdev);
>  }
>