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Mon, 06 Nov 2023 02:33:23 -0800 (PST) From: Jerome Brunet To: Thierry Reding , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao Subject: [PATCH 5/6] arm: dts: amlogic: migrate pwms to new meson8 v2 binding Date: Mon, 6 Nov 2023 11:32:52 +0100 Message-ID: <20231106103259.703417-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231106103259.703417-1-jbrunet@baylibre.com> References: <20231106103259.703417-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 06 Nov 2023 02:34:34 -0800 (PST) Update Amlogic based SoC PWMs to meson8-pwm-v2 compatible Signed-off-by: Jerome Brunet --- arch/arm/boot/dts/amlogic/meson.dtsi | 4 ++-- arch/arm/boot/dts/amlogic/meson8.dtsi | 16 +++++++++++++--- arch/arm/boot/dts/amlogic/meson8b-ec100.dts | 2 -- arch/arm/boot/dts/amlogic/meson8b-mxq.dts | 2 -- arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts | 2 -- arch/arm/boot/dts/amlogic/meson8b.dtsi | 16 +++++++++++++--- 6 files changed, 28 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi index 8e3860d5d916..80cc004ad5fe 100644 --- a/arch/arm/boot/dts/amlogic/meson.dtsi +++ b/arch/arm/boot/dts/amlogic/meson.dtsi @@ -83,14 +83,14 @@ i2c_A: i2c@8500 { }; pwm_ab: pwm@8550 { - compatible = "amlogic,meson-pwm"; + compatible = "amlogic,meson8-pwm-v2"; reg = <0x8550 0x10>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@8650 { - compatible = "amlogic,meson-pwm"; + compatible = "amlogic,meson8-pwm-v2"; reg = <0x8650 0x10>; #pwm-cells = <3>; status = "disabled"; diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi index 59932fbfd5d5..153b8fe9c506 100644 --- a/arch/arm/boot/dts/amlogic/meson8.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -450,10 +450,14 @@ analog_top: analog-top@81a8 { }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; reg = <0x86c0 0x10>; #pwm-cells = <3>; status = "disabled"; + clocks = <&xtal>, + <0>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; clock-measure@8758 { @@ -702,11 +706,17 @@ timer@600 { }; &pwm_ab { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + clocks = <&xtal>, + <0>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + clocks = <&xtal>, + <0>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts index 3da47349eaaf..cdd7d04db256 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts @@ -441,8 +441,6 @@ &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts index 7adedd3258c3..68f4f70f4f03 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts @@ -162,8 +162,6 @@ &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &uart_AO { diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts index 941682844faf..ff955b960688 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts @@ -347,8 +347,6 @@ &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi index 5198f5177c2c..6c91eda92e8b 100644 --- a/arch/arm/boot/dts/amlogic/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -404,10 +404,14 @@ analog_top: analog-top@81a8 { }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; reg = <0x86c0 0x10>; #pwm-cells = <3>; status = "disabled"; + clocks = <&xtal>, + <0>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; clock-measure@8758 { @@ -677,11 +681,17 @@ timer@600 { }; &pwm_ab { - compatible = "amlogic,meson8b-pwm"; + clocks = <&xtal>, + <0>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8b-pwm"; + clocks = <&xtal>, + <0>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { -- 2.42.0