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From:   fan <nifan.cxl@gmail.com>
Date:   Mon, 6 Nov 2023 10:27:32 -0800
To:     Jim Harris <jim.harris@samsung.com>
Cc:     Davidlohr Bueso <dave@stgolabs.net>,
        Jonathan Cameron <jonathan.cameron@huawei.com>,
        Dave Jiang <dave.jiang@intel.com>,
        Alison Schofield <alison.schofield@intel.com>,
        Vishal Verma <vishal.l.verma@intel.com>,
        Ira Weiny <ira.weiny@intel.com>,
        Dan Williams <dan.j.williams@intel.com>,
        Fan Ni <fan.ni@samsung.com>,
        "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] cxl/region: fix x9 interleave typo
Message-ID: <ZUkwFLIKCSLXTCmq@debian>
References: <CGME20231103201835uscas1p29ca7f76ed5e4c829bfb022a040202d73@uscas1p2.samsung.com>
 <169904271254.204936.8580772404462743630.stgit@ubuntu>
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On Fri, Nov 03, 2023 at 08:18:34PM +0000, Jim Harris wrote:
> CXL supports x3, x6 and x12 - not x9.
> 
> Fixes: 80d10a6cee050 ("cxl/region: Add interleave geometry attributes")
> Signed-off-by: Jim Harris <jim.harris@samsung.com>
> ---

Reviewed-by: Fan Ni <fan.ni@samsung.com>

>  drivers/cxl/core/region.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 6d63b8798c29..d295b3488e4a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -403,7 +403,7 @@ static ssize_t interleave_ways_store(struct device *dev,
>  		return rc;
>  
>  	/*
> -	 * Even for x3, x9, and x12 interleaves the region interleave must be a
> +	 * Even for x3, x6, and x12 interleaves the region interleave must be a
>  	 * power of 2 multiple of the host bridge interleave.
>  	 */
>  	if (!is_power_of_2(val / cxld->interleave_ways) ||
>