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([2402:7500:4ce:8d0c:a813:4d0:7247:8a5e]) by smtp.gmail.com with ESMTPSA id g23-20020a1709029f9700b001c625d6ffccsm7136099plq.129.2023.11.07.00.53.15 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Nov 2023 00:53:18 -0800 (PST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.7\)) Subject: Re: [PATCH 06/12] RISC-V: crypto: add accelerated AES-CBC/CTR/ECB/XTS implementations From: Jerry Shih In-Reply-To: <20231102051639.GF1498@sol.localdomain> Date: Tue, 7 Nov 2023 16:53:13 +0800 Cc: Paul Walmsley , palmer@dabbelt.com, Albert Ou , herbert@gondor.apana.org.au, davem@davemloft.net, andy.chiu@sifive.com, greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@kernel.org, bjorn@rivosinc.com, heiko@sntech.de, ardb@kernel.org, phoebe.chen@sifive.com, hongrong.hsu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Reply-To: 20231102051639.GF1498@sol.localdomain Content-Transfer-Encoding: quoted-printable Message-Id: <39126F19-8FEB-4E18-B61D-4494B59C43A1@sifive.com> References: <20231025183644.8735-1-jerry.shih@sifive.com> <20231025183644.8735-7-jerry.shih@sifive.com> <20231102051639.GF1498@sol.localdomain> To: Eric Biggers X-Mailer: Apple Mail (2.3445.9.7) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 07 Nov 2023 00:53:34 -0800 (PST) On Nov 2, 2023, at 13:16, Eric Biggers wrote: > On Thu, Oct 26, 2023 at 02:36:38AM +0800, Jerry Shih wrote: >> +static int ecb_encrypt(struct skcipher_request *req) >> +{ >> + struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(req); >> + const struct riscv64_aes_ctx *ctx =3D crypto_skcipher_ctx(tfm); >> + struct skcipher_walk walk; >> + unsigned int nbytes; >> + int err; >> + >> + /* If we have error here, the `nbytes` will be zero. */ >> + err =3D skcipher_walk_virt(&walk, req, false); >> + while ((nbytes =3D walk.nbytes)) { >> + kernel_vector_begin(); >> + rv64i_zvkned_ecb_encrypt(walk.src.virt.addr, = walk.dst.virt.addr, >> + nbytes & = AES_BLOCK_VALID_SIZE_MASK, >> + &ctx->key); >> + kernel_vector_end(); >> + err =3D skcipher_walk_done( >> + &walk, nbytes & AES_BLOCK_REMAINING_SIZE_MASK); >> + } >> + >> + return err; >> +} >=20 > There's no fallback for !crypto_simd_usable() here. I really like it = this way. > However, for it to work (for skciphers and aeads), RISC-V needs to = allow the > vector registers to be used in softirq context. Is that already the = case? The kernel-mode-vector could be enabled in softirq, but we don't have = nesting vector contexts. Will we have the case that kernel needs to jump to = softirq for encryptions during the regular crypto function? If yes, we need to have = fallbacks for all algorithms. -Jerry=