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From:   "Shradha Todi" <shradha.t@samsung.com>
To:     "'Manivannan Sadhasivam'" <manivannan.sadhasivam@linaro.org>
Cc:     <jingoohan1@gmail.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
        <robh@kernel.org>, <bhelgaas@google.com>,
        <krzysztof.kozlowski@linaro.org>, <alim.akhtar@samsung.com>,
        <linux-pci@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-samsung-soc@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <pankaj.dubey@samsung.com>
In-Reply-To: <20231027134849.GA23716@thinkpad>
Subject: RE: [PATCH] PCI: exynos: Adapt to clk_bulk_* APIs
Date:   Wed, 15 Nov 2023 12:10:33 +0530
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References: <CGME20231009062222epcas5p36768b75c13c7c79965b5863521361a64@epcas5p3.samsung.com>
        <20231009062216.6729-1-shradha.t@samsung.com>
        <20231027134849.GA23716@thinkpad>
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> -----Original Message-----
> From: Manivannan Sadhasivam =5Bmailto:manivannan.sadhasivam=40linaro.org=
=5D
> Sent: 27 October 2023 19:19
> To: Shradha Todi <shradha.t=40samsung.com>
> Cc: jingoohan1=40gmail.com; lpieralisi=40kernel.org; kw=40linux.com;
> robh=40kernel.org; bhelgaas=40google.com; krzysztof.kozlowski=40linaro.or=
g;
> alim.akhtar=40samsung.com; linux-pci=40vger.kernel.org; linux-arm-
> kernel=40lists.infradead.org; linux-samsung-soc=40vger.kernel.org; linux-
> kernel=40vger.kernel.org; pankaj.dubey=40samsung.com
> Subject: Re: =5BPATCH=5D PCI: exynos: Adapt to clk_bulk_* APIs
>=20
> On Mon, Oct 09, 2023 at 11:52:16AM +0530, Shradha Todi wrote:
> > There is no need to hardcode the clock info in the driver as driver
> > can rely on the devicetree to supply the clocks required for the
> > functioning of the peripheral. Get rid of the static clock info and
> > obtain the platform supplied clocks. The total number of clocks
> > supplied is obtained using the devm_clk_bulk_get_all() API and used
> > for the rest of the clk_bulk_* APIs.
> >
> > Signed-off-by: Shradha Todi <shradha.t=40samsung.com>
> > ---
> >  drivers/pci/controller/dwc/pci-exynos.c =7C 46
> > ++++++-------------------
> >  1 file changed, 11 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-exynos.c
> > b/drivers/pci/controller/dwc/pci-exynos.c
> > index 9e42cfcd99cc..023cf41fccd7 100644
> > --- a/drivers/pci/controller/dwc/pci-exynos.c
> > +++ b/drivers/pci/controller/dwc/pci-exynos.c
> > =40=40 -54,8 +54,8 =40=40
> >  struct exynos_pcie =7B
> >  	struct dw_pcie			pci;
> >  	void __iomem			*elbi_base;
> > -	struct clk			*clk;
> > -	struct clk			*bus_clk;
> > +	struct clk_bulk_data		*clks;
> > +	int				clk_cnt;
> >  	struct phy			*phy;
> >  	struct regulator_bulk_data	supplies=5B2=5D;
> >  =7D;
> > =40=40 -65,30 +65,18 =40=40 static int exynos_pcie_init_clk_resources(s=
truct
> exynos_pcie *ep)
> >  	struct device *dev =3D ep->pci.dev;
> >  	int ret;
> >
> > -	ret =3D clk_prepare_enable(ep->clk);
> > -	if (ret) =7B
> > -		dev_err(dev, =22cannot enable pcie rc clock=22);
> > +	ret =3D devm_clk_bulk_get_all(dev, &ep->clks);
> > +	if (ret < 0)
>=20
> Please use =21(ret) here and below to be consistent with the driver.
>=20

In this case, only negative values indicate failure. Hence we cannot use (=
=21ret) here.

> >  		return ret;
> > -	=7D
> >
> > -	ret =3D clk_prepare_enable(ep->bus_clk);
> > -	if (ret) =7B
> > -		dev_err(dev, =22cannot enable pcie bus clock=22);
> > -		goto err_bus_clk;
> > -	=7D
> > +	ep->clk_cnt =3D ret;
>=20
> Since clk_cnt is =22int=22, you can just use it directly instead of =22re=
t=22.
>=20

Thanks for this suggestion=21 Will take care in v2.

> >
> > -	return 0;
> > -
> > -err_bus_clk:
> > -	clk_disable_unprepare(ep->clk);
> > -
> > -	return ret;
> > +	return clk_bulk_prepare_enable(ep->clk_cnt, ep->clks);
> >  =7D
> >
> >  static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep)
> > =7B
> > -	clk_disable_unprepare(ep->bus_clk);
> > -	clk_disable_unprepare(ep->clk);
> > +	clk_bulk_disable_unprepare(ep->clk_cnt, ep->clks);
> >  =7D
> >
> >  static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
> > =40=40 -332,17 +320,9 =40=40 static int exynos_pcie_probe(struct
> platform_device *pdev)
> >  	if (IS_ERR(ep->elbi_base))
> >  		return PTR_ERR(ep->elbi_base);
> >
> > -	ep->clk =3D devm_clk_get(dev, =22pcie=22);
> > -	if (IS_ERR(ep->clk)) =7B
> > -		dev_err(dev, =22Failed to get pcie rc clock=5Cn=22);
> > -		return PTR_ERR(ep->clk);
> > -	=7D
> > -
> > -	ep->bus_clk =3D devm_clk_get(dev, =22pcie_bus=22);
> > -	if (IS_ERR(ep->bus_clk)) =7B
> > -		dev_err(dev, =22Failed to get pcie bus clock=5Cn=22);
> > -		return PTR_ERR(ep->bus_clk);
> > -	=7D
> > +	ret =3D exynos_pcie_init_clk_resources(ep);
> > +	if (ret < 0)
> > +		return ret;
> >
> >  	ep->supplies=5B0=5D.supply =3D =22vdd18=22;
> >  	ep->supplies=5B1=5D.supply =3D =22vdd10=22;
> > =40=40 -351,10 +331,6 =40=40 static int exynos_pcie_probe(struct
> platform_device *pdev)
> >  	if (ret)
> >  		return ret;
> >
> > -	ret =3D exynos_pcie_init_clk_resources(ep);
> > -	if (ret)
> > -		return ret;
> > -
> >  	ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep-
> >supplies);
> >  	if (ret)
>=20
> You need to disable_unprepare() clocks in error path here and above.
>=20

Thanks for pointing out=21 Will take care in v2.

> - Mani
>=20
> --
> =E0=AE=AE=E0=AE=A3=E0=AE=BF=E0=AE=B5=E0=AE=A3=E0=AF=8D=E0=AE=A3=E0=AE=A9=
=E0=AF=8D=20=E0=AE=9A=E0=AE=A4=E0=AE=BE=E0=AE=9A=E0=AE=BF=E0=AE=B5=E0=AE=AE=
=E0=AF=8D=0D=0A=0D=0A