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Date:   Wed, 15 Nov 2023 11:51:27 +0100
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Subject: Re: [PATCH] serial: sc16is7xx: address RX timeout interrupt errata
To:     Daniel Mack <daniel@zonque.org>, Hugo Villeneuve <hugo@hugovil.com>
CC:     gregkh@linuxfoundation.org, jirislaby@kernel.org,
        u.kleine-koenig@pengutronix.de, linux-serial@vger.kernel.org,
        linux-kernel@vger.kernel.org, Maxim Popov <maxim.snafu@gmail.com>,
        stable@vger.kernel.org
References: <20231114074904.239458-1-daniel@zonque.org>
 <20231114102025.d48c0a6ec6c413f274b7680b@hugovil.com>
 <140280a6-1948-4630-b10c-8e6a2afec2de@zonque.org>
From:   Lech Perczak <lech.perczak@camlingroup.com>
In-Reply-To: <140280a6-1948-4630-b10c-8e6a2afec2de@zonque.org>
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Hi Daniel,

W dniu 14.11.2023 o=C2=A016:55, Daniel Mack pisze:
> Hi Hugo,
>
> On 11/14/23 16:20, Hugo Villeneuve wrote:
>> On Tue, 14 Nov 2023 08:49:04 +0100
>> Daniel Mack <daniel@zonque.org> wrote:
>>> This devices has a silicon bug that makes it report a timeout interrupt
>>> but no data in FIFO.
>>>
>>> The datasheet states the following in the errata section 18.1.4:
>>>
>>>   "If the host reads the receive FIFO at the at the same time as a
>>>   time-out interrupt condition happens, the host might read 0xCC
>>>   (time-out) in the Interrupt Indication Register (IIR), but bit 0
>>>   of the Line Status Register (LSR) is not set (means there is not
>>>   data in the receive FIFO)."
>>>
>>> When this happens, the loop in sc16is7xx_irq() will run forever,
>>> which effectively blocks the i2c bus and breaks the functionality
>>> of the UART.
>>>
>>> From the information above, it is assumed that when the bug is
>>> triggered, the FIFO does in fact have payload in its buffer, but the
>>> fill level reporting is off-by-one. Hence this patch fixes the issue
>>> by reading one byte from the FIFO when that condition is detected.
>> From what I understand from the errata, when the problem occurs, it
>> affects bit 0 of the LSR register. I see no mention that it
>> also affects the RX FIFO level register (SC16IS7XX_RXLVL_REG)?
> True, the errata doesn't explicitly mention that, but tests have shown
> that the RXLVL register is equally affected.
>
>> LSR[0] would be checked only if we were using polled mode of
>> operation, but we always use the interrupt mode (IRQ), and therefore I
>> would say that this errata doesn't apply to this driver, and the
>> patch is not necessary...
> Well, it is. We have seen this bug in the wild and extensively
> stress-tested the patch on dozens of boards for many days. Without this
> patch, kernels on affected systems would consume a lot of CPU cycles in
> the interrupt threads and effectively render the I2C bus unusable due to
> the busy polling.
>
> With this patch applied, we were no longer able to reproduce the issue.
Could you share some more details on the setup you use to reproduce this? I=
'd like to try out as well.
>
>
> Thanks,
> Daniel

--=20
Pozdrawiam/With kind regards,
Lech Perczak