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Wed, 15 Nov 2023 15:03:10 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AFF39YW019798 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 15:03:09 GMT Received: from [10.111.175.193] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 15 Nov 2023 07:03:06 -0800 Message-ID: <26a7eb74-7f54-4ade-a761-ce08e85f2a93@quicinc.com> Date: Wed, 15 Nov 2023 10:03:04 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] dt-bindings: phy: Document sm8450 pcie phys as having 4 clocks Content-Language: en-US To: Johan Hovold CC: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Krzysztof Kozlowski , , , , References: <20231103230339.966792-1-quic_eberman@quicinc.com> From: Elliot Berman In-Reply-To: Content-Type: text/plain; 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Wed, 15 Nov 2023 07:05:23 -0800 (PST) On 11/15/2023 2:15 AM, Johan Hovold wrote: > On Fri, Nov 03, 2023 at 04:03:38PM -0700, Elliot Berman wrote: >> I noticed while running make dtbs_check that >> qcom,sm8450-qmp-gen3x1-pcie-phy and qcom,sm8450-qmp-gen4x2-pcie-phy have >> 4 clocks, not 5. There was also a typo for the 8450 bindings: >> s/gen3x2/gen4x2/. >> >> Update the bindings to reflect the correct number of required clocks. >> >> Cc: Dmitry Baryshkov >> Fixes: 505fb2541678 ("dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml") >> Signed-off-by: Elliot Berman >> --- >> .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 16 ++++++++++++++-- >> 1 file changed, 14 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> index 2c3d6553a7ba..1768f2016a9f 100644 >> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml >> @@ -128,6 +128,20 @@ allOf: >> reg: >> maxItems: 1 >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,sm8450-qmp-gen3x1-pcie-phy >> + - qcom,sm8450-qmp-gen4x2-pcie-phy >> + then: >> + properties: >> + clocks: >> + minItems: 4 >> + clock-names: >> + minItems: 4 >> + > > I'm not sure which tree you think you're looking at but this is clearly > not correct. > > The phy nodes in arch/arm64/boot/dts/qcom/sm8450.dtsi have five clocks > defined. > You're right, next now has 5 clocks for 8450. -next vs. tip of tree strikes me again :) I'll send out a fix for just the typo tomorrow/Friday when I do another sweep of dtbs_check (on next/master instead of torvalds/master). > Johan