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Wed, 15 Nov 2023 17:42:37 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AFHgaT9000825 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 17:42:36 GMT Received: from [10.216.42.195] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 15 Nov 2023 09:42:30 -0800 Message-ID: <6d4d959c-b155-471b-b13d-f6fda557cfe0@quicinc.com> Date: Wed, 15 Nov 2023 23:12:16 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 05/10] usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver To: Johan Hovold CC: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng , , , , , , , , , References: <20231007154806.605-1-quic_kriskura@quicinc.com> <20231007154806.605-6-quic_kriskura@quicinc.com> <14fc724c-bc99-4b5d-9893-3e5eff8895f7@quicinc.com> <04615205-e380-4719-aff1-f32c26004b14@quicinc.com> Content-Language: en-US From: Krishna Kurapati PSSNV In-Reply-To: Content-Type: text/plain; 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Wed, 15 Nov 2023 09:43:17 -0800 (PST) Hi Johan, > Are you sure there's no support for hs_phy_irq also in the "femto" PHYs > and that it's just that there is currently no driver support for using > them? > > And why is it defined if there is truly no use for it? > We had an internal sync up with HW folks and here is some baseline suggestions we received: If DP/DM interrupts are defined, then that is the preferred path to used, irrespective if HS Phy irq is defined or not / or whether it is Femto / QUSB2 target. There is no target that has femto phy but misses DP/DM today. For cases like sdm660/msm8998/msm8953/msm8956, these targets use hs_phy_irq only and don't rely on DP/DM. So we cannot remove the binding in entirety. > Also, if hs_phy_irq and dp/dm_phy_irq were mutually exclusive, why does > the following Qualcomm SoCs define all three? > HS Phy Irq is redundant or functionality is mutually exclusive in this case. If there are targets that define all three, then we need to update those to only utilize DP/DM interrupts. Regards, Krishna,